GAA Nanowire Stack Channel Selection With 3D Active Region
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in CMOS transistors is to selectively choose the number of nanosheet or nanowire channel strips without compromising the structural integrity of the device or adjacent devices, while preventing leakage current through non-selected semiconductor strips.
Innovation Solution
The technique involves defining a three-dimensional active region with a surface active area and depth, forming an auxiliary buffer layer over non-selected semiconductor strips, and using a gate structure that wraps around the selected channel strips to prevent current flow through non-selected strips by increasing resistance and creating a depletion effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor strips are etched out to select channel strips, then the number of channel strips can be controlled, but the structural integrity of the device is compromised
Solution Approach 1:
The patent extracts only the necessary portion of the semiconductor stack by defining a three-dimensional active region that extends to a specific depth, thereby selecting only the desired number of channel strips without removing entire strips. This allows channel selection while preserving the structural integrity of non-selected strips and adjacent devices.
Solution Approach 2:
The patent transitions from two-dimensional planar selection to three-dimensional depth-based selection by defining an active region with a specific depth extending from the surface. This vertical dimension enables precise control over which channel strips are activated without affecting adjacent structures in the lateral direction.
2Ease of manufacture
If all semiconductor strips are used as channel strips, then manufacturing is simplified, but leakage current cannot be prevented through non-selected strips
Solution Approach 1:
The patent applies different properties to different regions by creating a three-dimensional active region with specific depth, thereby assigning electrical activity only to selected channel strips within that region. Non-selected strips outside the active region maintain their structural integrity but remain electrically inactive, preventing leakage current while simplifying manufacturing.
3Speed
If the gate length is reduced to increase switching speed, then CMOS switching speed improves, but short-channel effects compromise current control
Solution Approach 1:
The patent moves from planar gate control to three-dimensional wrapped-around gate structures that extend vertically along the channel strips. This vertical dimension provides enhanced electrostatic control over the channel, compensating for the reduced gate length and preventing short-channel effects while maintaining high switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the individual selection of channel strips without etching out semiconductor strips, maintaining device integrity and preventing leakage current, thereby enhancing electrostatic control and switching speed.
Implementation Method 1
using a gate structure that wraps around the selected channel strips to prevent current flow through non-selected strips by increasing resistance and creating a depletion effect
Implementation Method 2
forming an auxiliary buffer layer over non-selected semiconductor strips, and using a gate structure that wraps around the selected channel strips to prevent current flow through non-selected strips by increasing resistance
Data Source
AI summary
The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.