Narrow Gate Width Transistors with Lower Impurity Concentration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are miniaturized, the reliability of MOS transistors decreases due to narrower gate widths and high impurity concentrations, leading to premature failure and performance degradation.
Innovation Solution
The semiconductor device includes two types of field effect transistors with different gate widths, where the second transistor has a narrower gate width and lower impurity concentration than the first, with impurities introduced in a controlled manner to prevent B mode failure and maintain high reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate width is reduced to miniaturize the transistor, then the device size is reduced, but the reliability deteriorates due to B mode failure in the gate oxide film
Solution Approach 1:
The patent applies different impurity concentrations to narrow and wide gate width transistors based on their specific reliability requirements. For miniaturized narrow gate width transistors, lower impurity concentrations are used to prevent B mode failure and maintain gate oxide reliability, while still achieving the miniaturization goal. This local differentiation allows size reduction without sacrificing reliability.
Solution Approach 2:
The patent changes the impurity concentration parameter as a function of gate width to resolve the size-reliability contradiction. By establishing that narrow gate width transistors use lower impurity concentrations, the patent enables continued miniaturization while preventing B mode failure, thus maintaining reliability even as device size is reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the degradation of reliability in narrow gate width transistors while maintaining acceptable drive performance, ensuring high reliability and performance consistency across the semiconductor device.
Implementation Method 1
impurities are introduced into the polysilicon as much as possible
Data Source
AI summary
Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.