Narrow Semiconductor Mesa for Reduced Power Loss
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Solution Overview
Problem
Current techniques for increasing emitter/source side charge carrier density in power semiconductor transistors are reaching the practical limits of semiconductor processing technology, limiting the reduction of on-state voltage drop and switching losses in vertical semiconductor devices.
Innovation Solution
The semiconductor device features a semiconductor body with laterally separated trenches and a mesa dividing structure comprising non-semiconductor material, allowing for the formation of narrow semiconductor mesas with a low aspect ratio, which increases charge carrier density by concentrating carriers of one type and facilitating their extraction, thereby reducing on-state voltage drop and switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If current techniques are used to increase emitter/source side charge carrier density, then power consumption is reduced, but semiconductor processing technology reaches practical limits
Solution Approach 1:
The patent transitions from planar device architecture to a vertical architecture with deep trenches extending into the substrate. This dimensional change allows the formation of narrow semiconductor mesas with aspect ratios greater than 10:1, enabling increased charge carrier density through vertical confinement rather than lateral scaling, thereby overcoming current processing limits while reducing power consumption
Solution Approach 2:
The patent fundamentally changes the aspect ratio parameter of the semiconductor mesa from conventional values to greater than 10:1 (vertical depth to lateral width). This parameter change enables the narrow mesa structure that concentrates charge carriers, increasing emitter/source side charge carrier density and reducing on-state voltage drop without requiring further lateral dimension reduction that would exceed processing capabilities
2Quantity of substance
If narrow semiconductor regions are formed, then charge carrier density is increased, but device fabrication complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into distinct vertical regions separated by deep trenches filled with dielectric material. This segmentation creates isolated narrow semiconductor mesas where charge carriers are confined, increasing local charge carrier density. The segmented structure also simplifies fabrication by allowing independent processing of each mesa region and reducing cross-contamination between adjacent devices
Data Source
AI summary
First and second trenches are provided in a semiconductor body. A mesa dividing structure is provided between the first and second trenches and comprises non-semiconductor material. A first semiconductor mesa is provided between the first trench and the non-semiconductor material of the mesa dividing structure. The first semiconductor mesa includes emitter, body and drift regions. The first and second trenches are formed by a masked etching technique with a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width that is less than the minimum trench separation distance.