Native-Width Processor Atomic Stores for Wider Data
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Solution Overview
Problem
Existing processors face challenges in ensuring atomicity when storing data wider than their natively supported data width, as multiple sequential store operations cannot guarantee complete data integrity in the presence of power failures or system crashes.
Innovation Solution
Implementing an atomic store to memory instruction that ensures all or none of the data is stored atomically, using a staging buffer and write combining buffer to manage data wider than the natively supported width, preventing interleaving with other operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple sequential store operations are used to store data wider than natively supported width, then the data can be stored in memory, but atomicity cannot be guaranteed in the presence of power failures or system crashes
Solution Approach 1:
The patent applies preliminary action by pre-allocating a staging buffer before the atomic store operation begins. This buffer is reserved specifically to hold the entire wide data value during the store operation, preventing any interleaving with other memory operations. The buffer is prepared in advance and its state is managed throughout the operation to ensure atomicity - either the entire data is stored or none is stored, even in case of power failures or system crashes.
2Reliability
If the natively supported data width is increased to store wider data atomically, then atomicity is guaranteed, but the device complexity and cost increase
Solution Approach 1:
The patent applies segmentation by dividing the wide data store operation into manageable portions that fit within the natively supported data width. The wide data is broken into segments that can be processed and stored sequentially through the native width interface, while the staging buffer holds the complete wide data value. This allows atomicity to be achieved through coordinated segment management rather than requiring the entire wide data path to be natively supported.
Solution Approach 2:
The staging buffer serves as an intermediary between the processor's native width storage operations and the wider data width requirement. It mediates the transfer by holding the complete wide data value and coordinating its transfer through multiple native-width operations, ensuring atomicity without requiring the processor itself to have native support for the wider data width.
3Device complexity
If sequential store operations are used without atomicity guarantees, then device complexity is reduced, but data integrity is compromised during power failures or system crashes
Solution Approach 1:
The staging buffer is pre-allocated and prepared before the atomic store operation begins, establishing a controlled environment for atomic data transfer. This preliminary setup ensures that the buffer is in a known good state and ready to hold the complete wide data value, preventing partial or corrupted stores even if power fails during the operation.
Solution Approach 2:
The staging buffer provides beforehand cushioning by serving as a protective buffer zone that prevents partial data writes to memory. By holding the complete wide data value in this controlled buffer before the actual memory write, the system cushions against potential failures - if power is lost during the operation, the buffer ensures that either the complete data is written or nothing is written, preventing corrupted partial writes to memory.
Data Source
AI summary
A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.