Natively Doped High-Resistance Substrate for Latch-Up Prevention
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Solution Overview
Problem
Current methods for preventing latch-up in CMOS circuits are inefficient due to high area consumption and require additional process steps, making them costly and impractical, especially as integrated circuit chips shrink in size.
Innovation Solution
The use of a natively doped region with high resistance to separate parasitic bipolar transistors or isolate them from injector regions, reducing the area required for latch-up prevention while maintaining robustness, by providing a higher resistance ratio compared to traditional well structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional well structures are used to separate parasitic bipolar transistors, then latch-up prevention is achieved, but area consumption increases
Solution Approach 1:
The patent changes the doping parameter of the substrate from uniformly doped to having a high-resistance region with different doping concentration. This parameter change creates a high-resistance path that prevents latch-up current flow while occupying minimal area, thus resolving the contradiction between reliability and area consumption
Solution Approach 2:
The patent introduces a localized high-resistance region in the substrate adjacent to the SCR structure. This local modification of substrate quality provides effective latch-up prevention only where needed, rather than requiring extensive well structures across the entire chip area
2Reliability
If guard rings and sufficient space are added to eliminate parasitic transistor gain, then latch-up is prevented, but device complexity increases
Solution Approach 1:
The patent extracts the latch-up prevention function from the complex system of guard rings and spaced transistors, and implements it through a simpler modification of the substrate doping profile. The high-resistance substrate region alone provides the necessary prevention without requiring additional guard ring structures or increased spacing
3Reliability
If parasitic SCRs are physically separated from injectors, then latch-up probability is reduced, but area consumption increases
Solution Approach 1:
The patent changes the substrate resistance parameter in the region between the SCR and injector to create a high-resistance path. This parameter modification effectively isolates the SCR from the injector electrically without requiring physical separation, thus preventing latch-up while minimizing area consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents latch-up with reduced area consumption and without additional process steps, enhancing the robustness and cost-effectiveness of semiconductor devices by achieving the necessary separation resistance in a smaller space.
Implementation Method 1
A natively doped region having a high resistance is formed in the substrate adjacent to the SCR structure
Data Source
AI summary
A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transistor that form the SCR, and/or to isolate the entire SCR from the injector source in order to prevent latch-up. The high resistance of the natively doped region allows to achieve the separation resistance needed in a smaller space, as compared to the space required to achieve the same separation resistance in a well. Accordingly, the invention provides for more robust and cost effective latch-up prevention devices.