Negative Capacitance Gate Stack for Subthreshold Swing Reduction
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Solution Overview
Problem
Current semiconductor technologies face challenges in improving subthreshold properties of transistors, particularly due to the negative capacitance effects in negative capacitance field effect transistors (NC-FETs) which can cause hysteresis and limit the reduction of subthreshold swing (SS) below desired thresholds.
Innovation Solution
A negative capacitance gate stack structure for FETs is introduced, featuring a first gate dielectric layer and a second gate dielectric layer made of ferroelectric materials, with the area ratio of the second gate dielectric layer to the first gate dielectric layer adjusted to enhance charge neutrality and reduce capacitance, thereby improving subthreshold properties without causing hysteresis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a negative capacitance field effect transistor (NC-FET) using a ferroelectric material is used to improve subthreshold properties, then the subthreshold swing is reduced, but hysteresis is caused
Solution Approach 1:
The gate electrode is divided into two separate gates (first gate and second gate) that can be independently controlled. This segmentation allows the first gate to provide the primary switching function while the second gate compensates for hysteresis effects, thereby reducing subthreshold swing without sacrificing reliability
Solution Approach 2:
The patent adjusts the thickness of the ferroelectric layer and the voltage applied to the second gate to optimize the negative capacitance effect. By carefully controlling these parameters, the subthreshold swing is reduced to below 60 mV/decade while minimizing hysteresis through precise parameter optimization
2Manufacturing precision
If the subthreshold swing is reduced below 60 mV/decade using NC-FET, then subthreshold properties are improved, but hysteresis effects become more pronounced
Solution Approach 1:
The second gate acts as an intermediary element that mediates the hysteresis effects generated by the ferroelectric material in the first gate. By applying an appropriate voltage to the second gate, it compensates for the hysteresis and allows the system to achieve sub-60 mV/decade subthreshold swing without the harmful hysteresis effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the subthreshold swing to less than 60 mV/decade, and further to 5 mV/decade by adjusting the area ratio, while maintaining the physical thickness of the second gate dielectric layer, thus enhancing the performance of NC-FETs without inducing hysteresis.
Implementation Method 1
a negative capacitance field effect transistor (NC-FET) using a ferroelectric material has been proposed
Implementation Method 2
a second gate dielectric layer made of ferroelectric materials
Data Source
AI summary
A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.