Negative Capacitance Material in Buried Channel DRAM Transistors
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Solution Overview
Problem
The read/write operation speed of buried-channel array transistors in DRAM devices is limited by the threshold voltage, leading to reduced on-current and decreased performance when it surpasses a certain limit.
Innovation Solution
Incorporating a negative capacitance material layer, such as ferroelectric materials like hafnium zirconium oxide, between the insulating and metal layers in the trench structure of the semiconductor device, which enhances the read/write operation speed by reducing gate-induced drain leakage and optimizing the thickness of the negative capacitance material layer for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the threshold voltage of the buried-channel array transistor is increased to improve integration density, then the on-current is reduced, but the read/write operation speed decreases
Solution Approach 1:
The patent introduces a negative capacitance material layer (ferroelectric layer) in the gate structure, which changes the electrical parameters of the transistor. This layer provides negative capacitance that amplifies the gate voltage, effectively reducing the threshold voltage and increasing the on-current without changing the physical dimensions of the device, thus maintaining integration density while improving speed
Solution Approach 2:
The gate structure is formed as a composite of multiple layers including the negative capacitance material layer (ferroelectric material), insulating layer, and metal layers. This composite structure combines the benefits of different materials: the ferroelectric layer provides negative capacitance for voltage amplification, the insulating layer provides electrical isolation, and the metal layers provide conductive pathways, collectively resolving the contradiction between threshold voltage and operation speed
2Speed
If a negative capacitance material layer is added to increase read/write operation speed, then leakage current is reduced, but device structure becomes more complex
Solution Approach 1:
The negative capacitance material layer is nested within the existing gate structure, specifically positioned between the insulating layer and the metal layers. This nested configuration allows the ferroelectric layer to be integrated into the conventional transistor architecture without requiring complete structural redesign, thus adding functionality while minimizing complexity increase
Solution Approach 2:
The negative capacitance material layer acts as an intermediary between the control gate and the channel, providing voltage amplification and reducing gate-induced drain leakage. This intermediary layer mediates the interaction between the gate and channel, enabling improved performance without direct modification of the channel structure itself
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of a negative capacitance material layer increases the read/write operation speed by enabling faster charging and discharging, reducing leakage current, and improving overall DRAM performance.
Implementation Method 1
a negative capacitance material layer, such as ferroelectric materials like hafnium zirconium oxide
Data Source
AI summary
A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.