Negative-Capacitance Gain-Peaking Receiver Stages for High Bandwidth
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Solution Overview
Problem
Conventional gain-peaking amplifiers for high-frequency serial I/O receivers face limitations in gain-bandwidth product, requiring significant increments in bias current and device size, and suffer from bandwidth reduction when cascaded, making them challenging for high-speed applications like 28 Gb/s chip-to-chip channels due to severe transmission-line loss and signal reflections.
Innovation Solution
The implementation of a gain-peaking amplifier stage comprising a source-degenerative transconductance stage, a negative capacitance unit, and a trans-impedance stage with LC resonant circuits, which boosts gain by canceling parasitic capacitance and using a controlled current source with high output impedance, allowing for cascaded stages with reduced bandwidth reduction and enhanced AC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional gain-peaking amplifiers are used to achieve high gain-bandwidth product, then bias current and device size must be significantly increased, but this increases power consumption and device complexity
Solution Approach 1:
The patent changes the electrical parameters of the amplifier by introducing a negative capacitance unit that modifies the frequency response characteristics. This allows the amplifier to achieve gain peaking without requiring proportional increases in bias current and device size, thereby resolving the contradiction between gain-bandwidth product and device complexity
Solution Approach 2:
The negative capacitance unit acts as an intermediary element that mediates between the input and output stages. It provides the necessary phase compensation and frequency response shaping without requiring direct increases in active device count or bias current, thus achieving high gain-bandwidth product with reduced device complexity
2Power
If multiple amplifier stages are cascaded to achieve higher gain, then the overall bandwidth is reduced, but this limits high-speed application performance
Solution Approach 1:
The patent modifies the frequency response parameters of each cascaded stage by incorporating negative capacitance units. This changes the pole-zero distribution in a way that reduces the bandwidth penalty typically associated with cascading multiple stages, thereby maintaining higher overall bandwidth while achieving the required gain
Solution Approach 2:
The negative capacitance units provide a form of frequency-dependent feedback that compensates for the bandwidth reduction effect of cascading. By introducing zeros that cancel the effect of cascaded poles, the overall bandwidth is preserved while the gain is multiplied across stages
3Power
If bias current is increased to improve gain-bandwidth product, then power consumption increases, but this is undesirable for high-speed serial I/O receivers
Solution Approach 1:
The patent changes the frequency response parameters through negative capacitance compensation rather than through bias current adjustment. This allows the gain-bandwidth product to be optimized by modifying the electrical characteristics of existing devices rather than by increasing power consumption
Solution Approach 2:
The patent substitutes the traditional approach of using increased bias current (analogous to increasing mechanical force) with an electrical parameter modification approach using negative capacitance. This replacement achieves the same performance improvement without the associated power consumption penalty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration supports high-speed data rates with improved gain-peaking and bandwidth characteristics, reducing power consumption and frequency range saturation, while providing flexibility in gain adjustment and immunity to process variations, effectively addressing the limitations of conventional designs.
Implementation Method 1
a negative capacitance unit, and a trans-impedance stage with LC resonant circuits, which boosts gain by canceling parasitic capacitance
Implementation Method 2
a trans-impedance stage with LC resonant circuits, which boosts gain by canceling parasitic capacitance
Data Source
AI summary
The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.