Programmable Negative Charge Pump for Deeper Voltage With Less Area
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Solution Overview
Problem
Charge pumps in non-volatile memory devices occupy significant chip area and consume high current, particularly for generating higher voltage levels, and this area requirement increases with each generation due to the growing number of memory cells, necessitating the generation of deeper negative voltage levels.
Innovation Solution
A negative voltage charge pump with reduced area requirements and lower current consumption is implemented, utilizing serially connected charge transfer switches and stage capacitors, which are controlled by non-overlapping clock signals to generate deeper negative voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional charge pumps are used to generate higher voltage levels, then the required voltage level is achieved, but chip area and current consumption increase significantly
Solution Approach 1:
The charge pump is divided into multiple stages, where each stage generates a specific voltage level. By segmenting the voltage generation into discrete stages (e.g., -5V, -10V, -15V), the system can achieve higher voltages through cumulative effect while keeping each individual stage compact, thereby reducing total chip area compared to a single-stage high-voltage generator.
Solution Approach 2:
The patent transitions from planar charge pump layouts to a three-dimensional stacked capacitor architecture. Capacitors are arranged in vertical stacks with multiple plates positioned at different height levels, utilizing the third dimension (vertical space) to increase capacitance density without occupying additional chip area, thus reducing the overall footprint of the charge pump circuit.
2Power
If conventional charge pumps generate deeper negative voltages, then voltage requirements are met, but current consumption increases
Solution Approach 1:
The charge pump employs periodic clock signals to control the switching of charge transfer elements. By using non-overlapping clock phases (e.g., PH0, PH1, PH2) that periodically activate different capacitor stages in sequence, the system efficiently transfers charge in discrete packets, minimizing current draw compared to continuous charge pumping methods while achieving the required negative voltage depth.
Solution Approach 2:
The patent dynamically adjusts operating parameters such as clock frequency and capacitor switching sequences based on the required voltage level. For deeper negative voltages, the system activates additional capacitor stages and optimizes charge transfer timing, allowing efficient scaling of voltage output without proportionally increasing current consumption.
3Quantity of substance
If more memory cells are added to increase storage capacity, then memory capacity improves, but charge pump area requirements increase
Solution Approach 1:
The charge pump circuit is designed with a universal multi-stage capacitor architecture that can serve multiple memory blocks simultaneously. The same charge pump structure supports both 2D and 3D memory cell arrays, and can generate various voltage levels (-5V, -10V, -15V) as needed by different memory operations, eliminating the need for separate charge pumps for each memory block and reducing overall area requirements.
Solution Approach 2:
The charge pump implements a nested capacitor configuration where smaller capacitance elements are integrated within larger voltage generation stages. The stacked capacitor plates are arranged in nested layers, with each layer contributing to the overall voltage multiplication effect. This nested structure maximizes voltage generation capability within a compact footprint, allowing the charge pump to support growing memory capacity without proportional area increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces chip area and current consumption while effectively generating the necessary negative voltage levels for non-volatile memory operations, improving efficiency and reducing power requirements.
Implementation Method 1
Charge pumps are important building blocks for NAND Flash memory and other non-volatile memory devices. They are commonly used for providing appropriate bias voltage levels
Implementation Method 2
A first capacitor of the set of stage capacitors has a first plate connected to a first input of the first charge transfer switch and a second plate connected to a second input of the first charge transfer switch
Data Source
AI summary
A charge pump with a programmable architecture generates a deeper negative voltage to reduce chip area requirements and lower current consumption at chip-level. A set of serially connected charge transfer switches are connected between an input node, that can be set at ground or other low voltage, and an output node providing the negative voltage. Stage capacitors each have one plate connected between a pair of the charge transfer switches and a second plate receiving one of a pair of non-overlapping clock signals having an amplitude of the charge pump supply level. The charge transfer switches receive control signals to be alternately on or off and, when off, the output of the charge transfer switch is shorted to its control gate. Different input voltage levels can be selected and used to pre-charge the control gate of the first of the charge transfer switches to provide different output nodes.