NEM Relay Memory Cells for Soft Error Upset Immunity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits with volatile memory elements are susceptible to soft error upsets caused by cosmic rays and radioactive impurities, leading to data corruption and making them unsuitable for applications requiring high reliability, such as remote telecommunications equipment.
Innovation Solution
The integration of nano-electromechanical (NEM) relay technology with complementary metal-oxide-semiconductor (CMOS) technology in integrated circuits, where nonvolatile relay switches are used to form memory cells that retain their state even without power, providing immunity to soft error upsets and zero standby current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If volatile memory elements are used in integrated circuits, then power consumption is reduced and writing is fast, but the memory elements are susceptible to soft error upsets caused by cosmic rays and radioactive impurities
Solution Approach 1:
The patent replaces traditional electronic memory elements with mechanical nano-electromechanical (NEM) relay switches. The NEM relay uses a mechanical switch mechanism with moving parts that open or close based on applied voltage, rather than relying on charge storage in capacitors or transistor states. This mechanical switching mechanism is inherently more resistant to soft error upsets from cosmic rays and radioactive impurities, as the mechanical state is not easily disturbed by ionizing radiation that affects electronic charge states.
2Reliability
If nonvolatile relay switches are used to form memory cells, then soft error upset immunity is achieved, but device complexity increases due to integration of NEM and CMOS technologies
Solution Approach 1:
The patent combines nano-electromechanical (NEM) relay technology with complementary metal-oxide-semiconductor (CMOS) technology in a single integrated circuit. The NEM relay switches are formed on top of CMOS devices and coupled through vias in a dielectric stack, creating a hybrid structure where the NEM layer provides radiation-hard memory storage and the CMOS layer provides control and readout functionality. This merging allows the benefits of both technologies to be realized while sharing common substrate and interconnect structures.
Solution Approach 2:
The patent implements a layered structure where the NEM relay switches are formed on top of the CMOS devices, with the NEM layer nested above the CMOS layer. The NEM relay switches include moving parts that are suspended over CMOS circuitry, creating a three-dimensional nested architecture. This nesting allows efficient use of space and enables the two different technology layers to interact through vertical vias while maintaining their respective functions.
3Duration of action of stationary object
If traditional volatile memory elements are used, then manufacturing is simpler, but data is lost when power is lost and standby current is required to maintain state
Solution Approach 1:
The patent replaces electronic charge-based memory storage with mechanical relay switch positions. The NEM relay switches maintain their state (open or closed) through their mechanical configuration rather than requiring continuous power to maintain charge states. This mechanical state persistence enables nonvolatile memory operation where data is retained without power, eliminating the need for refresh operations and standby current that plague volatile memory systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables integrated circuits to maintain data integrity in the presence of high-energy particle strikes, ensuring reliable operation and reduced power consumption, making them suitable for critical applications.
Implementation Method 1
The first and second nonvolatile relay switches may each include gate and bulk terminals and may retain their state even if the gate-to-bulk voltage is low
Data Source
AI summary
Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.