Nested IC Package System for High Density Integration
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Solution Overview
Problem
Existing integrated circuit packaging technologies struggle to cost-effectively reduce package dimensions while meeting the demands of increasing integration density, and existing package-on-package solutions often result in increased height due to the stacking of two ordinary packages.
Innovation Solution
A carrier with top and bottom sides, featuring edge and inner terminal pads, is used to connect and encapsulate an integrated circuit die, allowing for flexible stacking configurations without increasing package height by exposing outer terminal pads for further connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package-on-package stacking is used to increase integration density, then chip density is improved, but package height increases
Solution Approach 1:
The patent embeds a first integrated circuit die within a cavity of a second integrated circuit die, creating a nested configuration where one die is positioned inside the volume occupied by the other die. This nesting approach allows two dies to be integrated without simply stacking them vertically, thereby increasing chip density while maintaining a compact package height profile.
Solution Approach 2:
Instead of traditional vertical stacking that increases height in the Z-dimension, the patent utilizes the X-Y plane by creating a nested arrangement where one die is positioned within the footprint or lateral space of another die. This dimensional reconfiguration allows integration without proportionally increasing package height.
2Ease of manufacture
If conventional packaging methods are used to maintain manufacturing simplicity, then ease of manufacture is improved, but package dimensions cannot be reduced
Solution Approach 1:
The patent forms a cavity within the second integrated circuit die before the die is fully processed or packaged. This preliminary cavity formation allows subsequent embedding of the first die to occur during standard assembly processes, rather than requiring complex post-packaging operations. The cavity is prepared in advance using techniques such as selective removal of die material or formation during wafer-level processing, enabling size reduction without significantly complicating the manufacturing flow.
3Quantity of substance
If multiple integrated circuits are stacked to meet integration demands, then chip density is improved, but system level assembly yield decreases
Solution Approach 1:
The patent performs testing and validation of integrated circuit dies before they are embedded in the nested configuration. Known-good-die (KGD) selection and pre-assembly testing are conducted to ensure that only verified functional dies are combined in the nested structure. This preliminary quality assurance step prevents assembly yield losses that would occur if defective dies were discovered only after final package assembly.
Solution Approach 2:
The nested embedding configuration allows for integrated testing and validation during the assembly process itself. The first die can be tested electrically before embedding, and the nested structure facilitates access for testing without requiring complete disassembly. This integrated approach to testing within the nested architecture maintains assembly yield by enabling quality verification at appropriate stages.
Data Source
AI summary
An integrated circuit package system is provided forming a carrier having a top side and a bottom side, forming an edge terminal pad on the top side and an inner terminal pad on the bottom side, connecting an integrated circuit die to an inner portion of the edge terminal pad, and encapsulating the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed.