Nested Interposer Packaging With Self-Aligned Bump Pads

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Solution Overview

Problem

Current multi-die packaging architectures suffer from larger form factors and poor yield and reliability due to alignment issues and warpage when using traditional packaging substrates, particularly with interconnections between dies.

Innovation Solution

The use of heterogeneous nested interposers with cavities and nested components, where dies are connected to the interposer and nested components using interconnects that include bump pads for self-alignment, improving alignment and reliability even with fine-pitched interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional packaging substrates are used for multi-die integration, then dies can be connected together, but alignment issues and warpage occur resulting in poor yield and reliability

Engineering Contradiction:
Improveyield and reliabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

An interposer substrate is introduced as an intermediary component between multiple dies. The interposer provides a stable platform with precisely positioned bump pads that facilitate accurate alignment and electrical interconnection between dies, eliminating the alignment and warpage issues associated with traditional direct die-to-die bonding on packaging substrates.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The bump pads on the interposer are designed to enable self-alignment between the interposer and dies during the bonding process. This self-alignment mechanism reduces the need for complex external alignment equipment and procedures, improving both manufacturing precision and yield while maintaining reliability.

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If multi-chip integration architectures are used to increase performance, then functional capabilities are improved, but form factor increases making them unsuitable for some use cases

Engineering Contradiction:
Improveperformance capabilityVSAvoidform factor
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a traditional planar multi-chip arrangement to a three-dimensional stacked architecture where dies are vertically positioned on the interposer. This vertical stacking enables multiple chips to be integrated in the Z-dimension rather than spreading them out in the X-Y plane, significantly reducing the overall form factor while maintaining high performance capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer structure nests multiple functional components including bump pads, through-component vias, and embedded passive components within a compact volume. This nesting approach allows dense integration of multiple dies and supporting structures without proportionally increasing the external dimensions, thereby reducing form factor while preserving adaptability.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11824018B2Heterogeneous nested interposer package for IC chips
Publication Date: 2023.11.21 INTEL CORP
  • US11824018B2 patent drawing
  • US11824018B2 patent drawing
  • US11824018B2 patent drawing

AI summary

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.