Multi-Die Network Processor Package for Low-Latency Memory Access
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Solution Overview
Problem
Conventional solutions for data processing applications face limitations due to high cost and inefficient high latency external memory devices, which hinder performance in systems requiring fast access to large data structures and payload data.
Innovation Solution
The integration of network processors with low-latency memory devices in a multi-die single package system, utilizing a high-speed interface and network on chip (NOC) circuitry for efficient data exchange and dynamic reconfiguration, enabling sector-aligned memory as a temporary storage and cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external memory devices are used to provide high capacity memory, then memory capacity is improved, but memory latency increases and cost increases
Solution Approach 1:
The system is divided into multiple functional dies (network processor die, memory die, I/O die) that are packaged together in a single package. This segmentation allows each die to be optimized for its specific function while maintaining close physical proximity, thereby achieving high capacity through multiple memory dies while keeping latency low through short inter-die connections.
Solution Approach 2:
The patent transitions from a conventional two-dimensional planar arrangement to a three-dimensional stacked arrangement of multiple dies. This vertical stacking in the third dimension enables high capacity memory through multiple layers while maintaining low latency through short vertical interconnects, effectively resolving the capacity-latency tradeoff.
2Quantity of substance
If external memory devices are used to provide high capacity memory, then memory capacity is improved, but cost increases
Solution Approach 1:
Multiple functional components (network processor, memory, I/O interfaces) that would traditionally be separate external devices are merged into a single integrated package. This consolidation achieves high capacity through multiple memory dies while reducing overall system cost by eliminating the need for separate external memory devices and reducing system complexity.
3Loss of time
If multi-die single-package systems are implemented, then memory latency is reduced and bandwidth is increased, but device complexity increases
Solution Approach 1:
The multi-die single-package system implements a universal architecture that can support multiple network protocols and functions through a common high-speed interconnect fabric. This multi-functionality allows the system to achieve low latency and high bandwidth for various applications while managing complexity through a standardized, reusable architectural framework.
4Productivity
If multi-die single-package systems are implemented, then bandwidth is increased, but device complexity increases
Solution Approach 1:
A high-speed interconnect fabric acts as an intermediary between the network processor die and memory die, enabling high bandwidth data transfer. This intermediary component manages the complexity of direct high-speed connections by providing a standardized communication protocol and interface layer, thereby achieving high productivity while controlling system complexity.
Data Source
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AI summary
This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.