Neural Processor Clock Gating for Lower Parallel Compute Power
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Solution Overview
Problem
The challenge of high power consumption in neural processing units (NPUs) due to parallel operation of multiple compute units is not effectively addressed by existing technologies, limiting their efficiency in deep learning and inference tasks.
Innovation Solution
A neural processor with clock gating for multiple compute units based on a data flow architecture, utilizing a clock controller to selectively gate clock signals based on operation states, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple compute units are operated in parallel to increase computation efficiency, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signal to compute units is selectively enabled or disabled based on real-time operation states. The operation controller dynamically adjusts clock signal distribution to active compute units only, transforming the static power consumption model into a dynamic one that adapts to workload requirements, thereby reducing power consumption while maintaining computational throughput.
Solution Approach 2:
The patent applies local quality by enabling different compute units to have different clock signal states simultaneously. Instead of uniformly clocking all compute units, the system selectively provides clock signals only to compute units that are currently active and require processing, creating local operational differences that optimize both performance and power efficiency.
2Reliability
If clock signals are continuously provided to all compute units, then reliability is improved, but use of energy increases
Solution Approach 1:
The patent implements a feedback mechanism where the operation controller monitors the operation states of compute units and uses this information to control clock signal distribution. The controller receives feedback about which compute units are active and adjusts clock gating accordingly, ensuring that clock signals are provided only when and where needed, thus maintaining reliability while reducing energy consumption.
Solution Approach 2:
The patent extracts the clock signal distribution function from a static, universal approach and makes it selective and conditional. By separating the clock signal provision to only those compute units that require it, the system removes unnecessary clock signaling to inactive units, thereby reducing power consumption without compromising the operational reliability of active units.
3Use of energy by moving object
If clock gating is implemented to reduce power consumption, then use of energy is improved, but device complexity increases
Solution Approach 1:
The patent achieves power reduction through a universal clock gating mechanism that can be applied across multiple compute units using the same control logic. The operation controller serves multiple functions: monitoring operation states, determining activation status, and controlling clock signal distribution. This multi-functional approach reduces the need for separate control circuits for each compute unit, thereby limiting the increase in device complexity.
Data Source
AI summary
Provided are a neural processor, a neural processing device, and a clock gating method thereof, which perform clock gating for a plurality of compute units based on a data flow architecture, in which the neural processor includes at least one neural core that processes at least one task, and a clock controller that selectively gates, according to a data flow architecture of the at least one task, a clock signal provided to the at least one neural core.