Neural Network Computation Circuit Using Segmented Nonvolatile Weights
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Solution Overview
Problem
Conventional neural network computation circuits face challenges in maintaining current accuracy while reducing total current, leading to issues with linearity and power consumption, particularly due to the clamping of current flowing through resistance elements and the Von Neumann bottleneck in transferring weight coefficients.
Innovation Solution
A computation circuit unit and neural network computation circuit that utilize nonvolatile semiconductor storage elements to selectively provide current corresponding to input data and weight coefficients, with a configuration that includes multiple nonvolatile storage elements and transistors to manage current flow and separate weight coefficients into high-order and low-order bits, allowing for reduced cell current and improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If current flowing through resistance elements is reduced to lower power consumption, then power consumption is reduced, but current accuracy deteriorates due to clamping effects
Solution Approach 1:
The patent segments the weight coefficient into multiple bits (sign bit, exponent bits, mantissa bits) and stores them in separate nonvolatile memory elements. This segmentation allows independent optimization of current flow for each segment, enabling reduced total current while maintaining computational accuracy through the combined effect of segmented current contributions.
Solution Approach 2:
The patent introduces a hierarchical structure with different data lines (first data line for sign and exponent, second data line for mantissa) and separate nonvolatile memory elements for each component. This dimensional separation allows the system to manage current flow in multiple dimensions simultaneously, reducing overall power consumption while preserving precision through the multi-dimensional representation of weight coefficients.
2Productivity
If weight coefficients are transferred from memory to compute units, then computation can proceed, but time is consumed due to the Von Neumann bottleneck
Solution Approach 1:
The patent merges storage and computation functions by integrating nonvolatile memory elements directly into the compute unit. Weight coefficients are stored in nonvolatile memory elements that remain part of the computation circuit, eliminating the need to transfer weights between separate memory and compute units. This merging enables in-place computation while maintaining the benefits of nonvolatile storage.
Solution Approach 2:
The patent uses nonvolatile memory elements as intermediary components that bridge storage and computation. These memory elements serve as both storage locations for weight coefficients and active participants in the computation process, eliminating the Von Neumann bottleneck by removing the separation between memory and compute units.
3Measurement precision
If multiple nonvolatile storage elements are used to represent weight coefficients, then accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the weight coefficient representation into distinct components (sign bit, exponent bits, mantissa bits), each stored in separate nonvolatile memory elements. This segmentation provides a systematic approach to achieving high accuracy without overwhelming complexity, as each segment can be independently controlled and combined during computation.
Solution Approach 2:
The patent employs dynamic control mechanisms where selection transistors selectively connect different nonvolatile memory elements to data lines based on computational requirements. This dynamic switching capability allows the system to manage complexity by activating only the necessary memory elements for current computations while maintaining the full accuracy potential of all stored segments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses the antinomic issues of reducing current and maintaining accuracy, enabling a neural network computation circuit with reduced power consumption and large-scale integration by optimizing current flow and weight coefficient management.
Implementation Method 1
a first nonvolatile semiconductor storage element holds, as a resistance value, information of a positive weight coefficient
Implementation Method 2
a first selection transistor... a gate of the first selection transistor is connected to the word line... one terminal of the first nonvolatile semiconductor storage element and a drain terminal of the first selection transistor are connected
Data Source
AI summary
In a neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation on input data and connection weight coefficients, a computation circuit unit that expresses one connection weight coefficient includes a plurality of selection transistors and a plurality of nonvolatile variable resistance elements. The nonvolatile variable resistance elements each express a weight coefficient with a different weight. Each of the nonvolatile variable resistance elements holds information of an upper digit of an absolute value of a positive weight coefficient, information of a lower digit of the absolute value of the positive weight coefficient, information of an upper digit of an absolute value of a negative weight coefficient, or information of a lower digit of the absolute value of the negative weight coefficient.