Neural Network Engine MAC Architecture for SSD Power Constraints
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Solution Overview
Problem
Conventional Deep Neural Network (DNN) engines are unsuitable for applications in flash memory devices like Solid State Drives (SSDs) due to strict power, thermal, and cost constraints, making it difficult to maintain Uncorrectable Bit Error Rate (UBER) requirements as the number of bits in each memory cell increases.
Innovation Solution
A method and apparatus for performing DNN operations within strict power, thermal, and cost envelopes by using an integrated circuit with a neural network engine that includes multiply-and-accumulate circuits (MACs) and activation function modules (AFMs) to process DNN layers efficiently, allowing for the coupling of weight and bias values and performing multiply-and-accumulate operations until generating output-layer-sums.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DNN engines are used to process deep neural networks, then neural network operations can be performed, but power consumption, thermal generation, and device complexity exceed the strict envelopes required for flash memory devices
Solution Approach 1:
The patent segments the DNN processing into distinct functional blocks: input processing unit, multiple parallel MAC units for different layers, and output processing unit. Each MAC unit is independently configured to process specific layers, allowing the system to perform required neural network operations while minimizing overall power consumption by activating only necessary processing units.
Solution Approach 2:
The patent applies local quality by providing dedicated bias storage for each layer and configuring each MAC unit with specific weight and bias values appropriate for its designated layer. This localized configuration ensures that each processing unit operates efficiently with minimal power consumption while maintaining the reliability needed for UBER requirements.
2Adaptability or versatility
If conventional DNN engines with extensive interconnect logic are used, then complete DNN processing capability is achieved, but device complexity and transistor count increase beyond what is suitable for integrated flash memory controllers
Solution Approach 1:
The patent divides the DNN engine into segmented functional units: input processing unit, multiple parallel MAC units (first MAC unit for first hidden layer, second MAC unit for second hidden layer), and output processing unit. This segmentation provides complete DNN processing capability while keeping each unit simple and suitable for integration in flash memory devices.
Solution Approach 2:
The patent implements universal processing units that can handle multiple functions. Each MAC unit is designed to process different layers of the DNN by receiving appropriate weight and bias values, providing versatile DNN processing capability without requiring separate dedicated circuits for each layer, thus reducing overall device complexity.
3Productivity
If parallel MAC units with extensive interconnect logic are implemented, then processing speed for multiple DNN layers is improved, but thermal generation and power consumption exceed acceptable limits for flash memory applications
Solution Approach 1:
The patent segments processing across multiple parallel MAC units, each handling specific layers (first MAC unit for first hidden layer, second MAC unit for second hidden layer). This segmentation enables simultaneous processing of multiple layers, improving productivity while keeping each unit small enough to generate minimal heat, thus staying within thermal limits for flash memory devices.
Data Source
AI summary
A method for performing a neural network operation includes receiving weight and bias values of a deep neural network (DNN). An array of feature values, a bias value and a set of weight values for a single layer of the DNN are coupled to a neural network engine. Multiply-and-accumulate operations are performed on the single layer at one or more multiply and accumulate circuit (MAC) to obtain a sum corresponding to each neuron in the single layer. A layer output value corresponding to each neuron in the single layer is coupled to a corresponding input of the MAC. The coupling a bias value and a set of weight values, the performing multiply-and-accumulate operations and the coupling a layer output value are repeated to generate an output-layer-sum corresponding to each output-layer neuron and an activation function is performed on each output-layer-sum to generate DNN output values.