Neural Processing Unit Clock Phasing to Reduce Peak Power

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Solution Overview

Problem

The fluctuating supply voltage in neural processing units (NPUs) due to varying computational demands of artificial neural network layers leads to unstable power consumption and potential system malfunctions, particularly in low-power edge devices.

Innovation Solution

The implementation of a neural processing unit with a clock signal distribution mechanism that divides processing elements into groups, operating them with different clock phases to stabilize supply voltage and reduce peak power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of processing elements in the neural processing unit is increased to improve parallel processing performance, then the processing speed is improved, but the instantaneous power consumption and voltage fluctuation increase

Engineering Contradiction:
Improveparallel processing performanceVSAvoidinstantaneous power consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The processing elements are divided into multiple groups, with each group operating on a different clock phase. This segmentation allows the total power consumption to be distributed across different time phases, reducing peak power demands while maintaining overall processing throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different groups of processing elements are activated periodically with different clock phases. This periodic activation pattern ensures that not all processing elements consume power simultaneously, thereby reducing instantaneous power consumption while maintaining average processing performance.

Inventive Principle:
Principle #19Periodic action

2Productivity

If the number of processing elements is increased to enhance computational capability, then the computational speed is improved, but the supply voltage stability deteriorates

Engineering Contradiction:
Improvecomputational speedVSAvoidsupply voltage stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

Processing elements are segmented into multiple groups that operate on different clock phases. This segmentation distributes the electrical load across different time phases, preventing simultaneous current draws that would cause voltage drops and improve supply voltage stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The periodic activation of different processing element groups with different clock phases creates a staggered power consumption pattern. This periodic distribution of computational workload stabilizes the supply voltage by avoiding simultaneous high-current demands from all processing elements.

Inventive Principle:
Principle #19Periodic action

3Productivity

If all processing elements operate simultaneously to maximize throughput, then the productivity is improved, but the peak power consumption increases causing voltage drops

Engineering Contradiction:
ImprovethroughputVSAvoidpeak power consumption
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The processing elements are divided into multiple groups that operate in parallel but with different clock phases. This segmentation allows the system to maintain high throughput by keeping all processing elements active while distributing their power consumption across different time phases, thereby reducing peak power demands.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different groups of processing elements are activated in a periodic manner with different clock phases. This periodic action ensures that while all processing elements contribute to throughput, their power consumption is staggered in time, reducing the peak power consumption that would occur if all elements operated simultaneously.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250225381A1System being operated based on two or more different clock signals
Publication Date: 2025.07.10 DEEPX CO LTD
  • US20250225381A1 patent drawing
  • US20250225381A1 patent drawing
  • US20250225381A1 patent drawing

AI summary

A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.