Neural Processor Reconfigurable Data Paths Scalability
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Solution Overview
Problem
Current neural processing units face challenges in scalability and power efficiency due to predetermined data paths, which limit their ability to dynamically adjust to varying computational demands and lead to unnecessary power consumption and reduced efficiency.
Innovation Solution
A neural processor design that allows for reconfiguration of data paths by controlling controllable ports, enabling flexible data path configurations according to data flows and optimizing power usage by turning off unused cores or data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cores is increased to maximize computation efficiency, then computation efficiency is improved, but device complexity increases and scalability is reduced
Solution Approach 1:
The patent implements a universal data path structure where a single set of data paths can serve multiple computation cores through dynamic reconfiguration. The data paths are designed to be adaptable to different core configurations, allowing the same infrastructure to support varying numbers of cores without requiring dedicated data paths for each core, thereby reducing design complexity while maintaining computation efficiency.
Solution Approach 2:
The patent introduces dynamic reconfiguration capability that allows the data path topology to be adjusted based on the number of active computation cores. This dynamic adaptation enables the system to optimize its structure for the current workload, preventing the need for a fixed complex structure that would be required to support the maximum possible number of cores simultaneously.
2Device complexity
If data paths are predetermined to simplify design, then device complexity is reduced, but power consumption increases due to inability to dynamically adjust to computation demands
Solution Approach 1:
The patent implements dynamic data path reconfiguration that allows the system to activate only the data paths needed for current computation tasks. By transitioning from a static predetermined structure to a dynamic reconfigurable one, the system can power down unused data paths while maintaining design simplicity through the use of standardized reconfiguration mechanisms.
Solution Approach 2:
The patent changes the operational parameters of the data paths by enabling selective activation and deactivation of data path segments based on computation requirements. This parameter control allows the system to maintain a simple predetermined physical structure while dynamically adjusting its functional configuration to minimize power consumption.
3Ease of manufacture
If data paths are predetermined to reduce design complexity, then ease of manufacture is improved, but adaptability to varying computational demands is reduced
Solution Approach 1:
The patent designs universal data path components that can serve multiple functions and configurations. The predetermined structure uses standardized elements that can be dynamically reconfigured to adapt to different computational demands, combining manufacturing simplicity with operational versatility through multi-functional design.
Solution Approach 2:
The patent introduces dynamic reconfiguration capability into the predetermined data path structure, allowing the system to adapt its data flow topology based on computational requirements. This dynamic layer is added to the manufacturing-simple predetermined structure through reconfigurable switching elements that enable versatile data path arrangements without requiring complex custom manufacturing.
Data Source
AI summary
A processing device comprises a first set of processors comprising a first processor and a second processor, each of which comprises at least one controllable port, a first memory operably coupled to the first set of processors, at least one forward data line configured for one-way transmission of data in a forward direction between the first set of processors, and at least one backward data line configured for one-way transmission of data in a backward direction between the first set of processors. wherein the first set of processors are operably coupled in series via the at least one forward data line and the at least one backward data line.