Physical Realisation TRIZ Cases

A neural network processes conveyor logistics data using digital stopwatches that reset upon package detection to track temporal context.

A neural network quantization method retrieves statistical information from a reference layer to determine the quantization range for target layers.

Wordline noise switches inject proportional noise to train robust classifiers against adversarial attacks.

Calculates gradient differences during learning to adjust bit width, saving memory while maintaining accuracy.

Binary neuron clusters with multiplexers achieve fifty times energy efficiency gains over MAC designs.

Stacked sensor and processor wafers enable local analog preprocessing via crossbar arrays, eliminating energy-intensive data transmission to remote devices.

User equipment reports AI capabilities to generate encoder and decoder models for network deployment.

A neural network circuit uses a segmented broadcast bus to route data between neuro-blocks for parallel processing.

A neural network training system applies emulated non-uniform quantization using random noise to transform layer values.

A quantization method determines disruption limits for deep neural network weights to minimize arithmetic precision.

Winograd transforms lower computational resource usage and latency while maintaining image classification accuracy.

A neural network method selects specific neuron subsets to process input data efficiently.

Concatenated optical computing neural networks integrate in-field sensor measurements with simulation data to enhance fluid characterization accuracy.

A binarized neural network training method applies a parameterized weight clipping scheme to generate binarized weights.

Programmable thresholds prune neural network activations and weights to reduce computation cost while minimizing accuracy loss.

Selective activation of processing elements balances depth-wise and point-wise convolution engine throughput, reducing energy consumption in DSC accelerators.

A programmable look-up-table system uses Fused-Multiply-Add circuits to handle arbitrarily-spaced bins.

Micro-ring resonators execute linear transformations via signal mixing and phase tuning, reducing power consumption while increasing computational density.

A conductance balanced voltage pair ensures consistent memristive device changes for efficient neuromorphic circuit training.

A deployed neural network model uses a second higher accuracy model for online retraining to improve performance.

A deep learning algorithm compiling method adapts to hardware platforms through dynamic instruction processing.

Dynamic mode switching between compute and memory operations optimizes data flow, resolving bottlenecks in varied CNN layer requirements.

Asymmetric floating point formats optimize forward and backward propagation to reduce training time and power consumption.

Distributes partial data blocks to processing modules, reducing computational demands on source devices while maintaining privacy protection.

A neural processor reconfigures data paths via controllable ports to optimize resource usage.

Weighted least squares generates approximate polynomials for homomorphic encrypted neural network operations.

A neural network system reshapes model parameters to match dedicated hardware devices.

Satisfiability solver generates valid neural network configurations for hardware platforms.

A neural network training method replaces floating-point tensors with quantized inference data to align model weights with hardware constraints.

Optical signal transmission replaces electrical wiring for AI neuron communication, reducing latency and energy consumption during model parallelism.

Analog resistive processing unit arrays convert high-precision outputs to lower precision formats for dedicated digital update parameter calculations.

A single modulation layer diffractive neural network uses cyclic optical paths to perform deep learning computations with reduced physical footprint.

An activation function circuit extracts bit groups from arithmetic results to generate distribution signals for parallel processing.

An AI memory chip selects critical weight data subsets to reduce power consumption from external DRAM transfers.

Segmenting machine learning models into functional parts enables dynamic resource allocation, eliminating complete retraining time.

Conversion instructions transform 32-bit floating point values into 16-bit formats using existing execution circuitry.

An operation unit configures data bit width to match operator capabilities, enabling efficient neural network processing.

Segmenting neural network layers into classified tiles generates reusable assembly code, reducing software volume and system costs.

Optical processing chips execute matrix operations in parallel, reducing energy consumption and latency compared to digital electronics.

Replacing memristor cross-bars with analog op-amp circuits eliminates latency and leakage while enabling efficient edge computing.

Dynamic precision switching reduces processing time and energy consumption while maintaining output accuracy.

Assigns bit precision to AI model layers based on sensitivity metrics to balance accuracy and energy consumption.

Parallel data processing modules execute LSTM operations via dedicated vector instructions, reducing IO overhead and decoding power consumption.

A path-based neural network representation segments connections into independent input-output paths to reduce computational complexity.

Segmented DSP circuitry reduces area and power consumption while maintaining high bandwidth for machine learning operations.

Reversible graph neural networks partition vertex features to reduce memory complexity, enabling over 1000 layers on commodity GPUs.

A processor merges identical operation groups across neural networks into a shared group for single execution.

Segmented on-chip arithmetic parameter storage eliminates repeated external memory reads, accelerating computation speed in neural network processors.