Neuromorphic Memory Stack With Buffer for Faster Local Processing
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Solution Overview
Problem
Current main memory technologies, such as DRAM, face limitations in capacity, speed, and cost, necessitating advancements to meet increasing demand for efficient data processing and storage.
Innovation Solution
The integration of a neuromorphic layer between memory dies and a host interface, facilitated by a buffer that adjusts data speeds and reallocates connections to sub-channels, enables local processing and improved data throughput, enhancing the capabilities of memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional DRAM memory architecture is used, then manufacturing cost is reduced, but data processing speed and capacity are limited
Solution Approach 1:
The patent combines memory storage functions with neuromorphic processing functions into a single integrated device. The neuromorphic memory device merges synaptic weight storage with spike-based computation capabilities, allowing simultaneous data storage and neural network operations without requiring separate memory and processing components, thereby increasing data processing speed while controlling manufacturing costs through functional integration.
Solution Approach 2:
The neuromorphic memory device performs multiple functions including synaptic weight storage, spike generation, and neural network computation within a single device architecture. This multi-functionality eliminates the need for separate memory and processing units, improving overall system productivity while avoiding the increased manufacturing complexity that would result from multiple discrete components.
2Quantity of substance
If memory capacity is increased, then data storage capability is improved, but access speed decreases
Solution Approach 1:
The neuromorphic device acts as an intermediary between traditional memory and processing units, performing preliminary neural network computations locally. This intermediate processing reduces the amount of data that needs to be transferred and processed by the main CPU, effectively increasing access speed for neural network operations while maintaining large capacity for synaptic weight storage.
Solution Approach 2:
The patent transitions from traditional von Neumann architecture to a neuromorphic architecture that adds a temporal dimension to data processing through spike-based computation. This dimensional change allows parallel processing of multiple neural operations simultaneously, improving effective access speed while maintaining or increasing memory capacity for storing synaptic weights.
3Productivity
If neuromorphic processing is added, then data processing capability is improved, but device complexity increases
Solution Approach 1:
The neuromorphic memory device performs computations locally using stored synaptic weights without requiring external processing assistance. The device generates spikes autonomously based on incoming signals and stored weights, eliminating the need for complex external control circuitry and reducing overall system complexity while maintaining enhanced data processing capability.
Solution Approach 2:
The patent replaces traditional digital logic-based processing with analog-like continuous spike timing and amplitude-based computation. This substitution simplifies the device architecture by eliminating complex digital logic circuits in favor of simpler neural operation mechanisms that naturally perform computations through physical signal interactions.
Data Source
AI summary
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.