Neuromorphic Device Reference Cell Array Architecture
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Solution Overview
Problem
Current neuromorphic devices face challenges in improving integration density and reducing power consumption while maintaining accurate computations, particularly due to variations in conductivity of memory cells over time and temperature, which affect the accuracy of reference currents used in MAC operations.
Innovation Solution
The implementation of a neuromorphic device with a separate reference cell array and comparator circuit allows for accurate computation by comparing cell data with reference data, using quantized weights and zero point weights to improve integration density and power efficiency, and includes a logic circuit to generate and store quantized values, reducing the need for multiple reference cells and enhancing computation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate reference cell array is implemented to output reference current, then computation accuracy is improved, but device area increases
Solution Approach 1:
The reference cell array is designed to serve multiple functions: it provides reference currents for accurate MAC computation, enables compensation for conductivity variations in memory cells, and can be shared across multiple cell arrays. This multi-functionality allows the reference cell array to be integrated more efficiently, reducing the overall area increase while maintaining computation accuracy.
Solution Approach 2:
The patent implements a three-dimensional stacked architecture where cell arrays and reference cell arrays are vertically stacked. This dimensional change allows the reference cell array to be integrated within the same footprint as the cell arrays, significantly reducing the planar area increase while maintaining the benefits of separate reference current generation.
2Measurement precision
If multiple reference cells are used to ensure accurate reference current, then computation accuracy is improved, but power consumption increases
Solution Approach 1:
The reference cell array is activated periodically or on-demand rather than continuously. The system generates reference currents only when needed for computation, and the reference currents can be stored or buffered for use during computation, reducing the power consumption associated with continuously operating multiple reference cells.
Solution Approach 2:
The reference cell array serves multiple cell arrays and can be shared across different computational units. This universality allows a single reference cell array to support multiple functions, reducing the total number of reference cells needed and thereby reducing overall power consumption while maintaining accuracy.
3Quantity of substance
If quantized weights and zero point weights are used, then integration density is improved, but computation complexity increases
Solution Approach 1:
The quantization of weights and the determination of zero point values are performed in advance during the training phase or initialization. The quantized weights are pre-computed and stored in the memory cells, and the zero point values are pre-determined. This preliminary action simplifies the actual computation during inference, as the system only needs to perform multiplication and addition with the pre-quantized values, reducing computation complexity while achieving high integration density.
Data Source
AI summary
A neuromorphic device includes a plurality of cell tiles including a cell array including a plurality of memory cells storing a weight of a neural network, a row driver connected to the plurality of memory cells, and cell analog-digital converters connected to the plurality of memory cells and converting cell currents into a plurality of pieces of digital cell data, a reference tile including a plurality of reference cells, a reference row driver connected to the plurality of reference cells, and reference analog-digital converters connected to the plurality of reference cells and converting reference currents read via the plurality of reference column lines into a plurality of pieces of digital reference data, and a comparator circuit configured to compare the plurality of pieces of digital cell data with the plurality of pieces of digital reference data, respectively.