Neuromorphic Resistance Cell Array for Energy-Efficient Sum-of-Products
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Solution Overview
Problem
Current neuromorphic computing and machine learning systems face challenges in achieving high-speed sum-of-products operations while maintaining energy efficiency due to large arrays requiring high current consumption.
Innovation Solution
A device comprising an array of resistance cells with transistors and resistive elements, where the resistance cells have distinct resistance values based on transistor states, and peripheral circuits with lower on-resistance transistors, coupled with source, bit, and word lines, and sensing circuits to efficiently perform sum-of-products operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a very large array is used to perform many operations in parallel, then the computing speed and productivity are improved, but the total current consumption increases significantly
Solution Approach 1:
The large array is divided into multiple blocks, each with its own sense amplifier. This segmentation allows the system to activate only the necessary blocks for each computation, reducing the total current consumption while maintaining high computing speed through parallel operations in active blocks.
Solution Approach 2:
Instead of activating the entire large array, only the necessary portions (blocks) are activated for each specific computation. This partial action approach maintains high productivity by performing parallel operations in the activated blocks while significantly reducing overall current consumption by leaving other blocks inactive.
2Use of energy by moving object
If the resistance value of cells is increased to reduce current consumption, then the sensing current range becomes very small, making it difficult to detect and measure the current accurately
Solution Approach 1:
Sense amplifiers are introduced as intermediary devices between the high-resistance cells and the measurement system. These amplifiers boost the tiny sensing currents to measurable levels, making it possible to use high cell resistance values (reducing current consumption) while maintaining accurate current detection capability.
3Adaptability or versatility
If different sensing current ranges are required for different device architectures, then the device complexity increases due to the need for multiple sensing circuits
Solution Approach 1:
The sense amplifier is designed as a universal circuit that can handle different sensing current ranges through configuration options. This multi-functional design allows the same basic circuit architecture to serve multiple device architectures with different current ranges, avoiding the need for entirely separate sensing circuits for each architecture and thus reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables energy-efficient high-speed sum-of-products operations by optimizing resistance values and circuit designs, reducing power consumption while maintaining performance.
Implementation Method 1
Each of the plurality of resistance cells can comprise a resistive element and a transistor in series, wherein the transistor can have an on-state and an off-state, and the resistance cell can have a first resistance value when the transistor is in the on-state and a second resistance value when the transistor is in the off-state
Data Source
AI summary
An array of resistance cells has a number M of rows and a number N of columns of resistance cells. Each cell comprises a transistor having a threshold, representing a weight factor Wnm of the cell, and a resistive element in series with the transistor. Each cell has a cell resistance having a first value when the transistor is on and a second value when the transistor is off. A set of source lines is coupled to the resistance cells in respective columns. A set of bit lines is coupled to the resistance cells in respective rows, signals on the bit lines representing inputs x(m) to the respective rows. A set of word lines is coupled to gates of the transistors in the resistance cells in respective columns. Current sensed at a particular source line represents a sum of products of the inputs x(m) by respective weight factors Wnm.