Neuromorphic Unit Synapse Device Integrating Learning and Inference
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Solution Overview
Problem
Conventional neuromorphic devices require separate hardware units for learning and inference operations, leading to inefficiencies in area occupation and increased manufacturing processes due to the use of different memory devices like I-RRAM and CBRAM, which cannot be manufactured in the same process.
Innovation Solution
A neuromorphic device with a unit synapse array where both learning and inference operations are performed in the same stack structure, utilizing a cumulative stack portion and a through-hole portion with a via oxide layer and a common electrode, allowing for shared bit lines and reduced area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory devices (I-RRAM and CBRAM) are used for learning and inference operations, then each operation can be optimized for its specific function, but the device complexity and manufacturing process increase due to requiring different hardware units and separate manufacturing processes
Solution Approach 1:
The patent merges the learning unit and inference unit into a single integrated memory device structure. The learning unit includes a first functional metal layer and the inference unit includes a second functional metal layer, both within the same memory device, eliminating the need for separate hardware units and reducing device complexity while maintaining operational reliability for both functions
Solution Approach 2:
The memory device is designed with multi-functionality to perform both learning operations (using I-RRAM mechanism with reactive metal and metal oxide) and inference operations (using CBRAM mechanism with conductive filament formation). This universal design allows a single device to replace what previously required separate specialized devices, reducing overall system complexity
2Adaptability or versatility
If I-RRAM is used for learning operation, then wide variety of conductance states can be achieved through interfacial reaction, but preset conductivity state changes when power is removed
Solution Approach 1:
The patent segments the functional metal layers into two distinct types: a first functional metal layer for learning operations that utilizes reactive metal-metals oxide interfacial reactions to achieve diverse conductance states, and a second functional metal layer for inference operations that forms stable conductive filaments in metal oxide. This segmentation allows each layer to optimize for its specific operational requirement while both coexist in the same memory device structure
3Stability of the object's composition
If CBRAM is used for inference operation, then stable conductivity state is maintained when power is removed, but achievable conductivity is small
Solution Approach 1:
The patent segments the functional metal layers into two distinct types: a first functional metal layer for learning operations that utilizes reactive metal-metals oxide interfacial reactions to achieve diverse conductance states, and a second functional metal layer for inference operations that forms stable conductive filaments in metal oxide. This segmentation allows each layer to optimize for its specific operational requirement while both coexist in the same memory device structure
4Reliability
If separate learning unit and inference unit are implemented in different memory devices, then each unit can be optimized independently, but area occupation increases and manufacturing complexity increases
Solution Approach 1:
The patent merges the learning unit and inference unit into a single integrated memory device structure. The learning unit includes a first functional metal layer and the inference unit includes a second functional metal layer, both within the same memory device, eliminating the need for separate hardware units and reducing device complexity while maintaining operational reliability for both functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient implementation of both learning and inference operations in a single array, reducing area requirements and manufacturing complexity by integrating learning and inference devices within the same unit synapse device, ensuring accurate weight transfer and maintaining resistance states even when power is removed.
Implementation Method 1
a unit synapse device having both of a learning operation and an inference operation, the unit synapse device comprising a cumulative stack portion and a through-hole portion formed through the cumulative stack portion
Data Source
AI summary
Disclosed are a neuromorphic device and a unit synapse devices forming the same. The unit synapse device has a learning device and an inference device. The learning device and the inference device may share a via oxide layer and a common electrode, and a learning operation and an inference operation may be performed in one unit synapse device.