Neurosynaptic Core Block Transfer for Low-Latency Neuron Outputs
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Solution Overview
Problem
Existing neuromorphic systems face performance bottlenecks due to computationally hard arbitrary connectivity between neurons and axons, leading to power and energy consumption inefficiencies and latency issues in spike communication.
Innovation Solution
Implementing a neurosynaptic core architecture that time-multiplexes synaptic weights and neuron activations into blocks, allowing efficient block transfer and computation across logical cores, reducing power consumption and latency through block addressing and time-multiplexed access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If arbitrary connectivity between neurons and axons is implemented, then neural network flexibility is improved, but computational complexity and power consumption increase
Solution Approach 1:
The patent segments the neural network into multiple logical cores that can be mapped to physical cores. Each logical core has a restricted connectivity pattern (e.g., local connectivity within a core), avoiding the need to implement arbitrary global connectivity. This segmentation maintains neural network flexibility through multiple logical cores while reducing computational complexity by limiting each core's connectivity scope.
Solution Approach 2:
The patent introduces a logical-physical core mapping dimension, where multiple logical cores are mapped onto fewer physical cores. This dimensional transformation allows the system to achieve arbitrary connectivity at the logical level through software configuration while the physical hardware only needs to support limited local connectivity, thus resolving the contradiction between flexibility and complexity.
2Reliability
If spike communication is implemented between neurons and axons, then neural network functionality is improved, but latency increases
Solution Approach 1:
By segmenting the neural network into logical cores with local connectivity, the patent reduces the communication distance for spike signals. Neurons within the same logical core can communicate without long-distance transmission, maintaining neural network functionality while reducing latency associated with spike communication across the entire network.
Solution Approach 2:
The patent introduces logical cores as intermediaries between neurons and axons. These logical cores provide a structured communication framework that organizes spike transmission, allowing efficient routing and reducing unnecessary long-distance communications, thus maintaining functionality while reducing latency.
3Ease of operation
If neuron output values are transferred through data memory, then data accessibility is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple neuron output values into blocks that are transferred together through data memory. Instead of transferring individual neuron outputs separately, the system combines them into contiguous blocks, reducing the number of memory access operations. This merging approach maintains data accessibility while significantly reducing power consumption associated with repeated memory transfers.
Solution Approach 2:
The patent uses block copying mechanisms to transfer neuron output values efficiently. By copying contiguous blocks of data in single operations rather than individual values, the system maintains full data accessibility while reducing the overhead and power consumption of memory access operations.
4Measurement precision
If individual neuron processing is implemented, then processing precision is improved, but productivity decreases
Solution Approach 1:
The patent combines multiple individual neuron processing operations into block processing operations. Logical cores process blocks of neuron outputs simultaneously, maintaining the precision of individual neuron computations while achieving parallel processing throughput. This merging approach allows the system to preserve processing precision while dramatically improving computational productivity.
Solution Approach 2:
The patent enables continuous processing by organizing neurons into logical cores that can process data streams continuously. Instead of discrete individual neuron processing, the system maintains continuous flow of data through logical cores, preserving precision through systematic processing while maximizing productivity through uninterrupted computational action.
Data Source
AI summary
Block transfer of neuron output values through data memory for neurosynaptic processors is provided, which in some embodiments includes time-multiplexing. A neurosynaptic core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. Synaptic weights for one of a plurality of logical cores are read. The neurosynaptic core is configured to implement the one of the plurality of logical cores using the synaptic weights. At least one data block is provided as contiguous input activations to the neurosynaptic core. The input activations are processed by the neurosynaptic core to determine at least one contiguous block of output activations.