Neural Architectures TRIZ Cases

Joint tensor graph and recurrent networks capture cross-series structure and temporal dynamics for more accurate, memory-efficient forecasting.

Dedicated link memories store forward and candidate weights so multiple batches can run in parallel without waiting for weight updates.

Graph-based cell switching coordinates neighboring wireless cells to cut energy use while maintaining service quality under changing traffic loads.

A self-reset LIFR CMOS cell on PDSOI cuts neuromorphic IC footprint and power by replacing bulk SRAM- and comparator-based neuron designs.

Nonlinear weight quantization maps ANN weights to memristor conductance levels to cut rounding errors and improve analog MAC accuracy.

Compiler-added obfuscation layers mask neural network power, timing, and EM signatures to hinder side-channel model extraction.

Temporal differencing of 60 GHz radar frames helps machine learning detect human presence with fewer false alarms and lower power use.

By detecting sparsity and regrouping valid values before convolution, this case cuts wasted neural network computation and resource use.

A hybrid of gradient descent and gradient-free search finds better minima in non-convex neural network loss landscapes, reducing performance variance.

A domain-specific covariates block is retrained and the main AI block fine-tuned to improve forecasting when target-domain data is limited.

Runtime-configurable processor elements adapt to changing CNN tensor shapes while preserving ASIC-level speed and energy efficiency.

Pretrained LSTM models cut manual effort and training time for asset remaining useful life prediction while improving end-of-life accuracy.

Combined intra- and inter-kernel pruning compresses DNNs for real-time mobile inference while preserving accuracy and hardware regularity.

Time-multiplexed block transfer moves contiguous neuron outputs through memory to cut spike latency, data movement, and power use.

Physics-based neural layers infer optical parameters from limited measurements, enabling precise alignment and modeling without costly brute-force setup.

Configurable AMPA, NMDA, and GABA synaptic modules capture diverse spiking dynamics while improving adaptive signal processing efficiency.

An ANN-guided compiler selects DLA instruction strategies that ease memory and bandwidth bottlenecks to cut energy use and computation time.

Gated diode oscillators use feedback-loop switching and coupling to improve CMOS neural reliability, energy efficiency, and processing speed.

A storage-and-replay buffer preserves spiking neural state across idle periods, extending inference windows with lower memory area and power.

Gated-diode oscillators use feedback and coupling to improve CMOS-friendly reliability while reducing area for graph coloring and edge detection.

A state machine converts SNN event spikes into variable-length PWM signals, cutting switching activity while preserving low-latency control.

Historical secondary copy job data trains AI models to predict missed time thresholds and likely failures before data loss or backup delays occur.

Local in-memory neural computing cuts sensor-data transfer, energy use, and response time for factory hazard and anomaly detection.

Clustered representative KPIs cut neural network input size while preserving anomaly signals and supporting faster root cause analysis.

A metal ion-doped MIM neuron uses negative differential resistance to integrate and fire without a capacitor, cutting area and power.

Tiled convolution sections preserve image information at section boundaries while lowering memory use for large-image neural network processing.

By combining periodic patterns with long- and short-term load trends, this case improves peak prediction for cloud scheduling and lower redundancy.

Bit inversion and sign-based compression increase DNN data sparsity, cutting data movement, calculation time, and energy use.

Discretized neuron inputs and LUT-based operations obscure gradients, making auto-differentiation attacks on neural networks harder.

Linear bottlenecks and inverted residual blocks cut CNN operations and memory for mobile inference while preserving accuracy.

By comparing real and predicted measurement events, a WTRU can prioritize handover actions, reduce unnecessary reconfiguration, and improve NR resource use.

A matched feedback subcircuit preserves quantization error and blind-period inputs, improving signed neuron accuracy under PVT variation.

Machine learning links purchase intent, social ties, and buying history to surface knowledgeable contacts for more reliable purchase advice.

Dynamic learning rates matched to subnet complexity reduce weight interference and improve fairness in neural architecture search.

RL-guided NAS embeds neuromorphic hardware constraints into SNN search to cut search time and resource use while preserving accuracy and latency.

Time-dependent activation sparsity speeds diffusion model execution while preserving generation quality and lowering hardware and energy costs.

Multiple buffering times feed frequency images to a neural network, improving time-frequency analysis without manual window selection.

Shunting conductances near resting potential let one neuromorphic neuron perform multiplication-like integration with lower energy and richer dendritic computation.

Lateral inhibition in direction-tuned dendrite circuits separates motion patterns for low-power transient event detection with fewer false alarms.

Constrained RL-NAS searches SNN-ready architectures from raw data to meet neuromorphic hardware limits while preserving accuracy and NPU efficiency.

A compact quality code combines cut-to-cool time, transport conditions, and shelf-life loss to automate perishable cold-chain assessment.

Storage element pointers let a Neural Compute Engine remap tensors in place, supporting group and dilated convolutions without re-formatting overhead.

Context signals switch parameter sets in one neural network, improving task-specific accuracy while reducing network size and compute.

Sparse spiking encoder-decoder blocks approximate the Koopman operator for nonlinear systems with minimal data and far lower compute.

Encoded messages inside sensor input tokens let offline AI devices update neural network parameters without separate network links.

An SNN encoder-Koopman-decoder architecture approximates nonlinear dynamics with far lower compute and energy for real-time on-board use.

Structured sparsity prunes input matrices across deep network layers to cut inference time and computing overhead while preserving target precision.

A discretization layer converts continuous inputs into distance-preserving vectors, hardening neural networks against adversarial attacks without hurting performance.

Reusable neural processing graphs model brain-like function at multiple abstraction levels, enabling cognitive tasks on widely available computing resources.

Rate and synchrony neural coding with STDP learning improves sound feature extraction in spiking neural networks while lowering computation.