Neurosynaptic Network Interconnect Fabric for Scalable Chip Routing
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Solution Overview
Problem
Current neuromorphic and synaptronic computation systems face challenges in scaling multi-core neurosynaptic networks across chip boundaries, limiting their ability to efficiently exchange data and implement scalable neural networks.
Innovation Solution
The implementation of a system comprising multiple interconnected neurosynaptic core circuits with an interconnect fabric that tags data packets with routing information, enabling data exchange between network circuits through network interfaces, allowing for scalable neurosynaptic systems by routing address-event packets between chip circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-core neurosynaptic networks are scaled across chip boundaries, then the computational capacity and scalability of the system is improved, but the complexity of data exchange and interconnection between chips increases
Solution Approach 1:
The system is divided into multiple independent neurosynaptic core circuits, each capable of autonomous operation. Each core circuit contains neurons, axons, and synapses that can function independently, allowing the overall system to be scaled by adding more discrete core circuits across multiple chips rather than requiring a monolithic design.
Solution Approach 2:
Network interfaces are introduced as intermediary components between core circuits and the interconnect fabric. These interfaces handle data packet tagging, routing information addition, and protocol management, isolating the complexity of inter-chip communication from the core neurosynaptic circuits themselves.
2Productivity
If data exchange between network circuits is enabled through tagging and routing, then the efficiency of communication is improved, but the overhead of routing information and processing increases
Solution Approach 1:
Routing information is tagged onto data packets at the source network interface before transmission begins. This preliminary action of pre-tagging packets with destination information allows for efficient routing decisions at intermediate nodes without requiring complex real-time analysis or reconfiguration.
Solution Approach 2:
The routing information is copied onto each data packet as metadata, creating a self-contained routing instruction that travels with the data. This allows any node along the transmission path to make routing decisions based on the copied information without needing access to central control or complex lookup tables.
3Adaptability or versatility
If neurosynaptic core circuits are interconnected via an interconnect fabric, then the system's ability to implement large-scale neural networks is improved, but the loss of information during transmission across chip boundaries increases
Solution Approach 1:
The system employs acknowledgment and retransmission mechanisms where receiving nodes verify successful packet delivery and request retransmission if errors occur. This feedback loop ensures that information loss during inter-chip transmission is detected and corrected, maintaining data fidelity across the distributed neurosynaptic network.
Solution Approach 2:
Error detection and correction capabilities are built into the transmission protocol in advance, cushioning against potential information loss before it occurs. Checksum verification and redundant encoding are applied to data packets before transmission across chip boundaries, protecting against transmission errors.
Data Source
AI summary
Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.