NFET Extension Last Implants for ETSOI Series Resistance
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Solution Overview
Problem
Extremely thin silicon-on-insulator (ETSOI) devices face high series resistance issues due to their thin SOI layer, which degrades performance and increases leakage currents, necessitating improved junction designs for raised source/drain (RSD) epitaxy to reduce resistance and enhance link-up between source/drain and extension regions.
Innovation Solution
A method involving the formation of high quality nitride spacers, in-situ boron doped silicon germanium RSD, extension last NFET implants, and a metal-gate/high-k gate structure is employed to create a semiconductor structure with reduced series resistance and improved performance, including the use of rapid thermal anneals to activate NFET extension implants without diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If an extremely thin SOI layer is used in ETSOI devices, then leakage currents are reduced, but series resistance increases and performance degrades
Solution Approach 1:
The patent transitions from a planar source/drain structure to a raised source/drain (RSD) epitaxial structure that extends vertically into a third dimension. This dimensional change increases the cross-sectional area of the source/drain region, thereby reducing series resistance while maintaining the thin SOI layer for low leakage currents
Solution Approach 2:
The patent employs composite material structures including raised source/drain regions with specific doping profiles, extension regions with graded doping, and interface engineering between different material layers. These composite structures optimize both electrical conductivity and leakage characteristics simultaneously
2Reliability
If raised source/drain epitaxy is implemented, then series resistance is reduced, but junction design complexity increases
Solution Approach 1:
The patent divides the source/drain structure into distinct segments: the raised source/drain region, the extension region, and the link-up region. Each segment is independently optimized with specific doping profiles and geometries, allowing complex overall functionality to be achieved through simpler modular components
Solution Approach 2:
The patent applies different doping concentrations, material compositions, and structural characteristics to different local regions of the source/drain structure. For example, the extension region has a graded doping profile while the RSD region has a different doping concentration, optimizing performance locally in each region
3Power
If extension regions are added to improve link-up, then drive current is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions during the epitaxial growth process by forming the extension regions and doping profiles in advance, before subsequent processing steps. The extension last implant technique applies extensions finaly in the process sequence, ensuring proper doping distribution is established beforehand to facilitate drive current enhancement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces series resistance and enhances the performance of ETSOI devices by optimizing the junction design and activation of NFET extension implants, leading to improved drive current and reduced leakage currents.
Implementation Method 1
performing a short time scale anneal to activate the NFET extension implants but not diffuse them
Implementation Method 2
ion implanting extensions into the ETSOI underneath the at least one gate structure in the NFET portion
Data Source
AI summary
A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.