NFET Logic Gate Circuit for Low-Temperature 3D Integration
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Solution Overview
Problem
Conventional digital logic circuits manufactured using CMOS technology face limitations in integration due to high temperature requirements, restricting their application in back-end-of-line processes and hindering advancements in chip area reduction, power consumption, and performance improvement.
Innovation Solution
A logic gate circuit utilizing N-channel field-effect transistors (NFETs) with dual-gate structures, allowing for the implementation of logical '0' and '1' signals without requiring P-channel transistors, enabling integration in lower-temperature processes and reducing chip area by using NFETs for both pull-up and pull-down networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS technology is used to manufacture digital logic circuits, then the circuits can achieve basic logical relationships with stable performance, but the manufacturing process requires high temperature (about 1000°C) which limits integration in back-end-of-line processes
Solution Approach 1:
The patent changes the material parameter from conventional CMOS to oxide semiconductor, which fundamentally alters the manufacturing temperature requirement from high temperature (1000°C) to low temperature (below 450°C), enabling back-end-of-line integration while maintaining device functionality
Solution Approach 2:
The patent employs oxide semiconductor materials with specific properties (wide bandgap, high breakdown voltage) that combine the advantages of low-temperature processing with the electrical characteristics needed for reliable logic circuit operation, creating a composite solution that satisfies both thermal and performance constraints
2Reliability
If conventional CMOS logic gate circuits are used, then basic logical relationships can be implemented, but the chip area cannot be reduced and integration density is limited
Solution Approach 1:
The patent merges the pull-up and pull-down networks into a single NFET-based structure where the same transistor type performs both functions through dual-gate control, eliminating the need for separate PFET devices and reducing the overall circuit footprint
Solution Approach 2:
The NFET is designed with dual-gate functionality where it can operate in different modes (linear and saturation regions) to perform both pull-up and pull-down operations, making a single device type universal for both network functions and thereby reducing chip area
3Area of stationary object
If NFETs are used for both pull-up and pull-down networks, then chip area is reduced and back-end-of-line integration is enabled, but the circuit must operate reliably without P-channel transistors
Solution Approach 1:
The patent implements positive feedback through cross-coupled NFETs where the output of one gate feeds back to the input of another, creating stable bistable states that reliably maintain logical '0' and logical '1' outputs without requiring complementary transistor types
Solution Approach 2:
The patent utilizes the voltage-dependent characteristics of oxide semiconductor NFETs, switching between linear and saturation operation modes to achieve both pull-up and pull-down functionality, where parameter modulation (gate voltage control) replaces the need for different transistor types
Data Source
AI summary
A logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.