Nitride Semiconductor FET with Extraction Electrodes for Self Turn-On Suppression
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Solution Overview
Problem
Field effect transistors using nitride semiconductors face challenges with self turn-on and low static electricity resistance due to high gate-source charge quantity and switching delay, which are not adequately addressed by increasing gate-source capacitance alone.
Innovation Solution
A semiconductor device design that includes a substrate with stacked nitride semiconductor layers, a gate electrode, and active regions with carrier layers, where a gate extraction electrode and source extraction electrode are used to reduce gate-drain capacitance while maintaining or intermediate potential with the source extraction electrode, thereby reducing the Cgd/Cgs ratio and enhancing electrostatic discharge tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-source capacitance Cgs is increased to suppress self turn-on, then self turn-on is suppressed, but gate-source charge quantity Qgs increases causing increased gate drive loss and switching delay time
Solution Approach 1:
The device is divided into a first active region containing the main transistor and a second active region containing extraction electrodes. This segmentation allows the extraction electrodes to independently manage capacitance effects, enabling Cgs enhancement for self turn-on suppression while the extraction electrodes compensate for the resulting drive loss and delay through potential equalization.
Solution Approach 2:
The gate extraction electrode and source extraction electrode act as intermediary elements that mediate the capacitance effects. These extraction electrodes are positioned to equalize potentials with adjacent carrier layers, serving as intermediaries that balance the electrical distribution and reduce the harmful effects of increased Qgs on drive loss and switching speed.
2Reliability
If gate-source capacitance Cgs is increased to suppress self turn-on, then self turn-on is suppressed, but switching delay time increases
Solution Approach 1:
The device is divided into a first active region containing the main transistor and a second active region containing extraction electrodes. This segmentation allows the extraction electrodes to independently manage capacitance effects, enabling Cgs enhancement for self turn-on suppression while the extraction electrodes compensate for the resulting drive loss and delay through potential equalization.
Solution Approach 2:
The gate extraction electrode and source extraction electrode act as intermediary elements that mediate the capacitance effects. These extraction electrodes are positioned to equalize potentials with adjacent carrier layers, serving as intermediaries that balance the electrical distribution and reduce the harmful effects of increased Qgs on drive loss and switching speed.
3Area of moving object
If nitride semiconductor FET is designed to be smaller in size, then device size is reduced, but electrostatic resistance decreases causing self turn-on and low static electricity resistance
Solution Approach 1:
The invention extends the device structure in the vertical dimension by adding extraction electrodes in a second active region below the first active region. This dimensional extension allows electrostatic protection mechanisms to be added without increasing the planar footprint, thus maintaining small device size while improving electrostatic resistance through the extraction electrode potential equalization mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables high-speed operation of field effect transistors without malfunction and improves electrostatic resistance by reducing self turn-on and increasing ESD tolerance through optimized capacitance management.
Implementation Method 1
a high-concentration two-dimensional electron gas layer (2DEG layer) is generated at a junction interface by spontaneous polarization or piezoelectric polarization
Implementation Method 2
a high-concentration two-dimensional electron gas layer (2DEG layer) is generated at a junction interface by spontaneous polarization or piezoelectric polarization
Implementation Method 3
there is the following problem. Japanese Unexamined Patent Application Publication No. 2012-119625 discloses, for example, a method of forming an active region including a 2DEG layer between gate pad 810 and source pad 811
Data Source
AI summary
A semiconductor device includes: a substrate; a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than a band gap of the first nitride semiconductor layer; a first active region which includes a source electrode, a drain electrode, and a gate electrode, and has a first carrier layer located in the first nitride semiconductor layer; and a second active region which is on an extension of a long-side direction of the drain electrode and has a second carrier layer located in the first nitride semiconductor layer via an element isolation region, and a potential of the second carrier layer is substantially same as a potential of a source extraction electrode in the second active region or is an intermediate potential between a potential of a gate extraction electrode and the potential of the source extraction electrode opposite a short side of the drain electrode.