Nitride-Free Spacer for Embedded Flash Memory Charge Trapping
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Solution Overview
Problem
Split gate flash memory cells experience charge storage and removal anomalies due to the nitride spacer over the channel region, leading to undesired charge trapping and threshold voltage shifts over time, particularly with increased read and write operations.
Innovation Solution
Incorporating a nitride-free or oxide spacer in the sidewall recess of the charge-trapping layer nearest the source, which extends along the channel region and pushes the nitride sidewall spacer outwards, limiting undesirable charge trapping and maintaining stable threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a nitride spacer is used over the channel region, then the manufacturing process is simplified and alignment is easier, but charge trapping occurs leading to threshold voltage shifts and reduced reliability
Solution Approach 1:
The spacer structure is segmented into two distinct parts: a first spacer layer (nitride-free or oxide) positioned over the channel region, and a second nitride spacer layer positioned over the source region. This segmentation allows each layer to perform its specific function without interfering with the other, eliminating charge trapping while maintaining manufacturing simplicity
Solution Approach 2:
Different spacer materials are used in different locations: a nitride-free or oxide material is used specifically over the channel region where charge trapping must be prevented, while a nitride material is used over the source region where it provides beneficial alignment and spacing. This local differentiation optimizes both reliability and manufacturability
2Productivity
If read and write operations are increased to improve productivity, then data storage capacity is enhanced, but charge trapping anomalies increase leading to threshold voltage instability
Solution Approach 1:
By segmenting the spacer into a nitride-free/oxide layer over the channel and a nitride layer over the source, the structure enables high-speed read/write operations without the charge trapping that would otherwise accumulate with increased productivity, thus maintaining threshold voltage stability even with enhanced operational capacity
3Manufacturing precision
If a nitride spacer is used for alignment, then manufacturing precision is improved, but undesired charge trapping occurs reducing device performance
Solution Approach 1:
The spacer function is divided between two materials: the nitride-free or oxide first spacer layer eliminates charge trapping over the channel region, while the nitride second spacer layer provides the alignment precision benefit over the source region, thus achieving both manufacturing precision and eliminating harmful charge trapping
Solution Approach 2:
The solution applies different material properties locally: a non-charging material (nitride-free or oxide) is placed where charge trapping must be prevented (channel region), while a charging material (nitride) is placed where alignment precision is needed (source region), optimizing both aspects without compromise
Data Source
AI summary
In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.