Nitride Light-Emitting Element Tunnel Junction for Lower Forward Voltage

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Solution Overview

Problem

Nitride semiconductor light-emitting elements face challenges with increased forward voltage and reduced light emission output due to insufficient carrier supply through the tunnel junction.

Innovation Solution

The design includes a first n-side semiconductor layer with alternately arranged first barrier and well layers, where the thickness of third layers in the second group is less than that of the first group, increasing carrier supply to the active layer and optimizing the structure of the second active layer with similar layer arrangements to enhance light emission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a conventional tunnel junction structure is used, then the device complexity is reduced, but the forward voltage increases and light emission output decreases due to insufficient carrier supply

Engineering Contradiction:
Improvelight emission outputVSAvoidforward voltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The barrier layer is segmented into multiple sub-layers (first barrier sub-layer, second barrier sub-layer, and third barrier sub-layers) with different thicknesses. This segmentation allows optimization of carrier transport at different interfaces, improving light emission output while maintaining stable forward voltage through controlled carrier supply.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the barrier layer are assigned different thicknesses to achieve local optimization. The third barrier sub-layers have varying thicknesses to create localized potential well structures that enhance carrier supply at critical interfaces, resolving the contradiction between output and voltage stability.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the barrier layer thickness is increased, then the carrier supply to the active layer is improved, but the forward voltage increases

Engineering Contradiction:
Improvecarrier supplyVSAvoidforward voltage
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The barrier layer structure is designed with dynamic thickness variation through the third barrier sub-layers, creating a graded potential profile. This dynamic structure optimizes carrier supply by forming potential wells that facilitate carrier transport while controlling the energy barrier, thereby reducing forward voltage despite increased carrier supply.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The thickness parameter of the barrier layer is changed across different regions (first, second, and third barrier sub-layers) to optimize carrier transport. By varying the thickness parameter locally, the structure achieves improved carrier supply without proportionally increasing forward voltage, as the thinner third sub-layers create favorable potential conditions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240332450A1Nitride semiconductor light-emitting element
Publication Date: 2024.10.03 NICHIA CORP
  • US20240332450A1 patent drawing
  • US20240332450A1 patent drawing
  • US20240332450A1 patent drawing

AI summary

A nitride semiconductor light-emitting element includes: a first n-side semiconductor layer; a first active layer disposed on the first n-side semiconductor layer and comprising first barrier layers and first well layers alternately arranged; a first p-side semiconductor layer disposed on the first active layer; a second n-side semiconductor layer disposed on and in contact with the first p-side semiconductor layer; a second active layer disposed on the second n-side semiconductor layer; and a second p-side semiconductor layer disposed on the second active layer. The first barrier layer comprises layers including a first layer located closest to the first n-side semiconductor layer, a second layer located closest to the first p-side semiconductor layer, and a plurality of third layers located between the first layer and the second layer.