Nitride Semiconductor Device With Asymmetric Layer Thickness
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Solution Overview
Problem
In vertical nitride semiconductor devices, the 2DEG carrier density at the AlGaN/GaN heterojunction interface is reduced due to polarization effects, leading to increased on-resistance and decreased breakdown voltage due to parasitic bipolar transistors.
Innovation Solution
A nitride semiconductor device configuration with a C-plane substrate, where the third nitride semiconductor layer has a greater thickness on the side wall of the opening than on the flat section, and a p-type semiconductor layer is introduced to increase the threshold for normally off operation, reducing on-resistance and excluding parasitic bipolar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the third nitride semiconductor layer is made thinner to reduce device complexity, then manufacturing precision is improved, but carrier density decreases and on-resistance increases
Solution Approach 1:
The patent applies local quality by making the third nitride semiconductor layer thicker at the side wall of the opening (Gx) compared to the flat section (Gy). This localized thickness variation maintains high carrier density at the critical heterojunction interface where the opening is formed, while keeping the overall layer structure manageable. The side wall region specifically benefits from increased thickness to prevent carrier density degradation.
Solution Approach 2:
The patent transitions from uniform thickness control to asymmetric thickness control by introducing different thickness measurements in different spatial dimensions. The layer thickness is measured both parallel to the C-plane (Gx, side wall direction) and perpendicular to the C-plane (Gy, flat section direction), creating a three-dimensional thickness profile that optimizes carrier density while maintaining manufacturing feasibility.
2Reliability
If the third nitride semiconductor layer is made asymmetric (Gx > Gy) to maintain carrier density, then on-resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The asymmetric thickness design (Gx > Gy) applies local quality by specifically thickening the layer at the opening side wall region where carrier density is most critical. This localized approach targets the precise area needed for performance optimization without unnecessarily complicating the entire layer structure.
Solution Approach 2:
The patent explicitly introduces asymmetry in the layer thickness design, where the thickness parallel to the C-plane (Gx) is greater than the thickness perpendicular to the C-plane (Gy). This asymmetric configuration is deliberately designed to maintain carrier density at the heterojunction interface while managing the trade-off with manufacturing precision requirements.
3Reliability
If a p-type semiconductor layer is added to increase threshold for normally off operation, then breakdown voltage is enhanced, but device complexity increases
Solution Approach 1:
The p-type semiconductor layer acts as an intermediary element between the AlGaN electron supply layer and the GaN drift layer. This intermediate layer with p-type conductivity (achieved through Mg doping) serves as a buffer that increases the threshold voltage for normally off operation and enhances breakdown voltage, while integrating smoothly into the existing heterostructure.
Solution Approach 2:
The patent changes the conductivity parameter of the semiconductor layer by introducing p-type doping (Mg doping) in the third nitride semiconductor layer. This parameter change from n-type or undoped to p-type conductivity fundamentally alters the electrical characteristics, enabling normally off operation and improving breakdown voltage without requiring a complete redesign of the device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration effectively reduces on-resistance and enhances breakdown voltage by maintaining high carrier density and suppressing parasitic bipolar transistor operation, resulting in improved performance of the nitride semiconductor device.
Implementation Method 1
a high concentration of two-dimensional electron gas (2DEG) occurs at the heterointerface due to spontaneous polarization and piezoelectric polarization
Implementation Method 2
a high concentration of two-dimensional electron gas (2DEG) occurs at the heterointerface due to spontaneous polarization and piezoelectric polarization
Data Source
AI summary
A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.