Nitride Semiconductor Device With Dual Barrier Interfaces
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Solution Overview
Problem
Existing nitride semiconductor devices, such as HEMTs, face challenges with low response speed when turned off due to delayed disappearance of the two-dimensional electron gas (2DEG) and floating potential of the p-type semiconductor layer, leading to gate-leakage current issues.
Innovation Solution
A nitride semiconductor device is designed with a first and second interface between the gate electrode and the p-type semiconductor layer, where the second interface has a higher barrier than the first, allowing the depletion layer to spread and retract effectively, suppressing gate-leakage current and enhancing response speed by connecting the p-type semiconductor layer to the gate electrode earlier when turned off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single interface between the gate electrode and the p-type semiconductor layer is used, then the structure is simple, but the response speed when turned off is low due to delayed potential drop of the p-type semiconductor layer
Solution Approach 1:
The interface between the gate electrode and the p-type semiconductor layer is segmented into two distinct interfaces: a first interface with a first barrier height and a second interface with a second barrier height. This segmentation allows the depletion layer to spread from the second interface into the p-type semiconductor layer, causing the potential of the p-type semiconductor layer to drop earlier when the device is turned off, thereby improving the response speed without significantly complicating the overall device structure.
2Object-generated harmful factors
If the depletion layer spreads to the p-type semiconductor layer, then gate-leakage current is suppressed, but the potential of the p-type semiconductor layer becomes floating when turned off
Solution Approach 1:
The patent applies local quality by creating two interfaces with different barrier heights at different locations between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier height that allows the p-type semiconductor layer to remain electrically connected to the gate electrode, preventing floating potential. The second interface has a second barrier height that enables the depletion layer to spread into the p-type semiconductor layer, suppressing gate-leakage current. This local differentiation of barrier heights resolves the contradiction between suppressing leakage current and maintaining potential stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a high response speed when turned off while effectively suppressing gate-leakage current by ensuring the p-type semiconductor layer's potential drops earlier, improving the nitride semiconductor device's switching performance.
Implementation Method 1
a first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode.
Data Source
AI summary
A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type semiconductor layer located on the second nitride semiconductor layer; and a gate electrode located on the p-type semiconductor layer. A first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second barrier is higher than the first barrier.