Nitride Semiconductor Device Interconnection Stacking
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Solution Overview
Problem
Horizontal power-electronics semiconductor devices with a multi-finger structure experience significant switching losses due to parasitic capacitance between interconnections and the substrate, limiting their high-frequency and high-power applications despite their high breakdown field strength and electron mobility.
Innovation Solution
The semiconductor device incorporates a nitride semiconductor layer with strategically positioned interconnections, where the distance between the third interconnection and the nitride semiconductor layer is larger than the first interconnection, reducing parasitic capacitance while maintaining high electron mobility and breakdown voltage, and utilizing a polyimide or benzocyclobutene interlayer insulating film to minimize substrate-source parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a multi-finger structure is used to increase gate width for large current driving, then the current driving capability is improved, but the parasitic capacitance between interconnections and substrate increases causing large switching loss
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar interconnection layout to a three-dimensional stacked configuration. Multiple interconnections are arranged in different vertical layers (first interconnection layer, second interconnection layer, third interconnection layer) at different heights above the substrate. This vertical stacking separates interconnections that would otherwise be coplanar and closely spaced, thereby reducing parasitic capacitance while preserving the multi-finger structure's current driving capability.
Solution Approach 2:
The patent segments the interconnection system into multiple distinct layers, with each layer containing specific interconnections (first, second, third, and fourth interconnections) at different vertical positions. This segmentation allows independent optimization of each layer's routing and spacing, reducing overall parasitic capacitance while maintaining the necessary electrical connections for high-current operation.
2Reliability
If interconnections are placed closer to the nitride semiconductor layer to reduce resistance, then the electrical resistance is reduced, but the parasitic capacitance between interconnections and substrate increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension to separate the trade-off between resistance and capacitance. Interconnections in lower layers (first and second interconnection layers) can be positioned closer to the nitride semiconductor layer to minimize resistance, while interconnections in upper layers (third interconnection layer) are positioned farther away to minimize parasitic capacitance. This multi-layer approach allows simultaneous optimization of both electrical resistance and parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, increasing the semiconductor device's efficiency and operational speed while maintaining high breakdown field strength and electron mobility, suitable for high-frequency power semiconductor applications.
Implementation Method 1
utilizing a polyimide or benzocyclobutene interlayer insulating film to minimize substrate-source parasitic capacitance
Data Source
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AI summary
A semiconductor device according to an embodiment includes a nitride semiconductor layer, a plurality of source electrodes provided on the nitride semiconductor layer, a plurality of drain electrodes, a plurality of gate electrodes, a first interconnection having a first distance from the nitride semiconductor layer and electrically connecting the source electrodes, a second interconnection electrically connecting the gate electrodes, and a third interconnection having a third distance from the nitride semiconductor layer and electrically connecting the drain electrodes. Each of the drain electrodes are provided between the source electrodes. Each of the gate electrodes are provided between each of the source electrodes and each of the drain electrodes. The third distance is larger than the first distance.