Group-III Nitride Semiconductor Device Strain Management
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Solution Overview
Problem
Field effect transistors (FETs) with group-III nitride semiconductors face degradation when high voltages are applied between the gate and drain due to lattice relaxation and dislocation generation, leading to reduced device reliability and increased strain energy.
Innovation Solution
A semiconductor device with a buffer layer and electron supply layer formed in a specific growth mode parallel to the [0001] or [000-1] crystallographic axis, where the A-axis length on the group-III atomic plane side is larger than on the group-V atomic plane side, and the electron supply layer has a bandgap greater than the channel layer, offsetting internal strain and strain deviation to inhibit device degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage is applied between gate and drain, then device performance is improved, but lattice relaxation and dislocation generation occur leading to device degradation
Solution Approach 1:
The patent changes the crystallographic growth orientation from conventional <0001> to <11-20> direction, which fundamentally alters the lattice structure and strain distribution characteristics. This parameter change enables the device to withstand higher voltages without lattice relaxation and dislocation generation, resolving the contradiction between power performance and reliability
Solution Approach 2:
The patent employs a composite layered structure with alternating InAlN and AlN layers forming a superlattice. This composite material approach allows precise control of strain distribution and band structure, enabling high voltage operation while preventing degradation through the engineered heterostructure
2Ease of manufacture
If conventional growth mode is used, then manufacturing is simplified, but strain energy accumulates leading to device degradation
Solution Approach 1:
The patent modifies the growth orientation parameter to <11-20> direction and implements a superlattice structure with specific layer thicknesses (InAlN: 2-10nm, AlN: 2-10nm). These parameter changes enable strain management that prevents energy accumulation while remaining compatible with existing MOCVD or MBE growth techniques
Solution Approach 2:
The electron supply layer is segmented into multiple thin layers (InAlN and AlN alternating) rather than a single thick layer. This segmentation distributes and manages strain energy throughout the structure, preventing accumulation while maintaining ease of manufacture through standard epitaxial growth processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the degradation commencement voltage to 360 V, enhancing device reliability and maintaining high electron mobility, even under high voltage conditions.
Implementation Method 1
a layer existing on the group-III atomic plane side of the channel layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer
Implementation Method 2
offsetting internal strain and strain deviation
Data Source
AI summary
A semiconductor device including a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] crystallographic axis over a substrate and having a source electrode and a drain electrode, those being coupled electrically to the channel layer, and a gate electrode formed over the electron supply layer, in which, in the buffer layer and the electron supply layer, a layer existing on the group-III atomic plane side of the channel layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer; and the electron supply layer has a bandgap larger than the channel layer.