Nitride Semiconductor Superlattice Acceptor Activation

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Solution Overview

Problem

Nitride semiconductor layers face challenges in activating acceptors, leading to low activation rates and performance degradation due to deep levels, which affect the performance of semiconductor devices such as power FETs by increasing leakage current and threshold voltage issues.

Innovation Solution

A semiconductor device is designed with a superlattice layer formed by a laminated structure of nitride semiconductor layers with different band gaps, where the concentration of acceptors is higher in the layer with a smaller band gap, enhancing the activation rate and reducing deep level formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If uniform concentration of conductive impurities is introduced into both layers of the superlattice structure, then manufacturing is simplified, but the activation rate of acceptors remains low due to mismatch with band gap differences

Engineering Contradiction:
Improvesimplicity of impurity introductionVSAvoidactivation rate of acceptors
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by creating different impurity concentration profiles in different regions of the nitride semiconductor layer. Specifically, the concentration of conductive impurities (acceptors like Mg) is varied through the thickness of the layer, with higher concentrations near the interface with the layer having smaller band gap and lower concentrations in regions with larger band gap. This local variation optimizes acceptor activation in each region while minimizing deep level formation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes physical and chemical parameters of the nitride semiconductor structure, specifically the band gap difference between laminated layers and the spatial distribution of acceptor concentrations. By optimizing these parameters, the patent suppresses deep level formation and reduces leakage current while maintaining necessary p-type conduction properties.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9536978B2Semiconductor device
Publication Date: 2017.01.03 RENESAS ELECTRONICS CORP
  • US9536978B2 patent drawing
  • US9536978B2 patent drawing
  • US9536978B2 patent drawing

AI summary

To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.