Group IVA Nitride Charge Trapping Layer for SOI Substrate Loss

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Solution Overview

Problem

High resistivity semiconductor-on-insulator wafers used in RF devices suffer from parasitic power losses and device nonlinearity due to charge inversion or accumulation layers at the buried oxide/handle interface, which existing methods fail to effectively trap, maintaining substrate resistivity and improving device performance.

Innovation Solution

A multilayer structure is formed with a Group IVA nitride layer on a semiconductor handle substrate, selected from carbon nitride, silicon carbon nitride, or their combination, which acts as a charge trapping layer between the high resistivity substrate and the buried oxide, enhancing charge trapping efficiency by deep energy level defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high resistivity semiconductor-on-insulator wafers are used in RF devices, then substrate resistivity is maintained, but parasitic power losses and device nonlinearity occur due to charge inversion or accumulation layers at the buried oxide/handle interface

Engineering Contradiction:
Improvesubstrate resistivityVSAvoidparasitic power losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

A charge trapping layer is introduced as an intermediary between the buried oxide layer and the handle substrate. This layer actively traps charges that would otherwise form inversion or accumulation layers at the interface, preventing the harmful electrical effects while maintaining the high resistivity of the substrate. The charge trapping layer acts as a mediator that captures and immobilizes charges, thereby eliminating parasitic power losses and device nonlinearity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a charge trapping layer is added to the multilayer structure, then charge trapping efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvecharge trapping efficiencyVSAvoidmultilayer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The charge trapping layer is localized specifically at the critical interface region between the buried oxide and the handle substrate, where charge accumulation causes the most harm. Rather than modifying the entire device structure, the solution applies a targeted local modification only where needed. This approach improves charge trapping efficiency at the problematic interface while minimizing the overall complexity increase, as the additional layer is confined to a specific location rather than being distributed throughout the entire device.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The Group IVA nitride layer effectively traps charges, maintaining high resistivity even in the near-surface region, reducing parasitic power losses and harmonic distortions, thereby improving the performance of RF devices.

Implementation Method 1

A charge trapping layer is formed on the semiconductor handle substrate... The charge trapping layer effectively traps charges, maintaining high resistivity even in the near-surface region

Methodology Applied
Scientific EffectCharge trapping:

Data Source

PatentUS11183420B2High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
Publication Date: 2021.11.23 GLOBALWAFERS CO LTD
  • US11183420B2 patent drawing
  • US11183420B2 patent drawing

AI summary

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.