Integrated NMOS Half-Bridge Layout for Unified Gate Fabrication
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Solution Overview
Problem
Conventional buck power stage circuits with separate manufacturing processes for upper and lower gate power devices have limited application range and high manufacturing costs.
Innovation Solution
An NMOS half-bridge power device integrating an NMOS upper and lower gate devices is manufactured using a unified process, incorporating shared ion implantation and etching steps to form isolation regions and gates, allowing simultaneous formation of both devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate manufacturing processes are used for upper gate and lower gate power devices, then device performance can be optimized independently, but manufacturing cost increases and application range is limited
Solution Approach 1:
The patent merges the manufacturing processes for upper gate and lower gate power devices into a single integrated process. Both devices are formed simultaneously on the same semiconductor substrate using shared ion implantation and etching steps, eliminating the need for separate manufacturing processes while maintaining device performance through unified process control
Solution Approach 2:
The patent creates a universal manufacturing process that can produce both upper gate and lower gate power devices using the same ion implantation and etching parameters. The process is designed to handle multiple device types simultaneously, making the manufacturing system multi-functional and applicable to various power device configurations
2Reliability
If separate manufacturing processes are used for upper gate and lower gate power devices, then each device can be optimized, but manufacturing complexity and time increase
Solution Approach 1:
The patent combines multiple manufacturing steps into a single integrated process flow. Ion implantation and etching operations that were previously performed separately for upper and lower gate devices are now executed simultaneously using the same process equipment and parameters, reducing overall process complexity
Solution Approach 2:
The patent performs preliminary structuring of the semiconductor substrate before device fabrication, creating regions that will later form upper and lower gate devices. This preliminary action simplifies subsequent manufacturing steps by pre-defining device locations and characteristics, reducing the complexity of the main fabrication process
3Reliability
If separate manufacturing processes are used for upper gate and lower gate power devices, then device-specific requirements can be met, but productivity decreases
Solution Approach 1:
The patent merges the production of upper gate and lower gate power devices into a single manufacturing run. Both device types are fabricated simultaneously on the same substrate using identical ion implantation and etching processes, doubling the manufacturing throughput compared to separate processes while maintaining device-specific performance characteristics
Solution Approach 2:
The patent ensures continuous manufacturing operation by performing all ion implantation and etching steps in a single uninterrupted process sequence. The manufacturing line remains active throughout the entire fabrication process without idle time between producing upper and lower gate devices, maximizing productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration reduces manufacturing costs and expands application range by enabling the simultaneous formation of NMOS upper and lower gate devices, enhancing electrical isolation and efficiency.
Implementation Method 1
a first N-type high voltage isolation region and a second N-type high voltage isolation region, which are formed in the semiconductor layer of the NMOS upper gate device region by one same ion implantation process; a first N-type high voltage well and a second N-type high voltage well, which are formed in the semiconductor layer of the NMOS upper gate device region and the semiconductor layer of the NMOS lower gate device region, respectively, by one same ion implantation process; a first P-type high voltage well and a second P-type high voltage well, which are formed in the semiconductor layer of the NMOS upper gate device region and the semiconductor layer of the NMOS lower gate device region, respectively, by one same ion implantation process
Implementation Method 2
a first drift oxide region and a second drift oxide region, which are formed, by one same etching process including etching a drift oxide layer, in the NMOS upper gate device region and in the NMOS lower gate device region, respectively; a first gate and a second gate, which are formed, by one same etching process including etching a polysilicon layer, in the NMOS upper gate device region and in the NMOS lower gate device region, respectively
Data Source
AI summary
An NMOS half-bridge power device includes: a semiconductor layer, a plurality of insulation regions, a first N-type high voltage well and a second N-type high voltage well, which are formed by one same ion implantation process, a first P-type high voltage well and a second P-type high voltage well, which are formed by one same ion implantation process, a first drift oxide region and a second drift oxide region, which are formed by one same etch process including etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process including etching a poly silicon layer, a first P-type body region and a second P-type body region, which are formed by one same ion implantation process, a first N-type source and a first N-type drain, and a second N-type source and a second N-type drain.