NMOS LDO Regulator Gate Boosting for Fast Transient Response
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Solution Overview
Problem
Conventional PMOS LDO regulators face challenges with transient response, current capability, and area occupancy due to the need for large compensation capacitors, especially in modern integrated circuits with limited space and varying input power supply voltages.
Innovation Solution
An LDO regulator using an NMOS transistor with a gate boosting circuit and a precharge circuit to enhance the control signal for the NMOS transistor, allowing immediate response to transient load variations and reducing the need for large compensation capacitors by using a switching capacitor boosting scheme and a decoupling capacitor to minimize ripples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PMOS transistor is used in the LDO regulator, then high-impedance current mirror circuit can be achieved, but the regulator cannot be implemented in a standard CMOS process
Solution Approach 1:
The patent copies the functionality of the PMOS current mirror using NMOS transistors with adjusted biasing conditions. The NMOS transistor M3 replicates the current mirroring function traditionally performed by PMOS devices, enabling the LDO regulator to be implemented in standard CMOS process while maintaining the essential current mirror operation.
Solution Approach 2:
The patent changes the operating parameters of the NMOS transistor, specifically setting the gate-source voltage Vgs3 to be greater than the threshold voltage Vth by a controlled amount. This parameter adjustment allows the NMOS device to operate in the saturation region and perform current mirroring effectively, compensating for the typically lower output impedance of NMOS compared to PMOS devices.
2Measurement precision
If the gate-source voltage Vgs3 of the NMOS transistor is increased to improve current mirroring accuracy, then the output impedance decreases
Solution Approach 1:
The patent introduces dynamic control of the gate-source voltage Vgs3 through a control circuit that adjusts the bias voltage based on operating conditions. This dynamic adjustment optimizes the trade-off between current mirroring accuracy and output impedance, allowing the system to adapt to different load and input voltage conditions rather than using a fixed bias voltage.
Solution Approach 2:
The patent implements a feedback mechanism where the performance of the current mirror is monitored and the gate-source voltage Vgs3 is adjusted accordingly. The control circuit uses feedback from the regulator operation to optimize the NMOS transistor biasing, maintaining high current mirroring accuracy while compensating for output impedance variations.
3Adaptability or versatility
If an existing LDO regulator is redesigned to use NMOS transistors, then standard CMOS process can be used, but the output impedance significantly decreases
Solution Approach 1:
The patent creates a composite transistor structure by combining NMOS transistors with specific circuit topologies and biasing arrangements. This composite approach uses multiple NMOS transistors in configuration (including the series connection of M3 and M4) to achieve equivalent or improved output impedance performance compared to traditional PMOS implementations, while maintaining CMOS process compatibility.
Solution Approach 2:
The patent addresses the output impedance limitation by operating the NMOS transistor in a different region of its characteristic curves, specifically ensuring Vgs3 > Vth with controlled overdrive. This dimensional change in the operating point compensates for the inherently lower output impedance of NMOS devices compared to PMOS, achieving the required performance in standard CMOS process.
Data Source
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AI summary
A low dropout (LDO) regulator includes an NMOS transistor, a resistor ladder, an error amplifier and a gate boosting circuit. The NMOS transistor is configured for receiving an input voltage to generate an output voltage. The resistor ladder, coupled to the NMOS transistor, is configured for generating a feedback signal according to a level of the output voltage. The error amplifier, coupled to the resistor ladder, is configured for receiving the feedback signal from the resistor ladder to generate a control signal. The gate boosting circuit, coupled between the NMOS transistor and the error amplifier, is configured for boosting the control signal to control the NMOS transistor, so as to pull the output voltage to a target level.