NMOS Voltage Regulator Circuit for Fast Settling and High PSRR
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Solution Overview
Problem
Existing voltage regulator circuits face challenges in achieving fast settling times and good power supply rejection ratio (PSRR) while being constrained by size and overhead current limitations, particularly when using PMOS-based designs that require large capacitors.
Innovation Solution
Implementing a voltage regulator circuit using a negative-channel metal-oxide semiconductor (NMOS) instead of a positive-channel metal-oxide semiconductor (PMOS), coupled with a reference voltage circuit and a voltage inversion circuit, which eliminates the need for large capacitors at the output and enhances isolation, thereby achieving fast settling and superior PSRR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a PMOS-based voltage regulator is used, then the circuit can provide current to the load, but the circuit requires large capacitors which increases area and reduces settling speed
Solution Approach 1:
The patent changes the fundamental parameter of the power transistor from PMOS to NMOS. This parameter change enables the voltage regulator to achieve fast settling times without requiring large output capacitors, as NMOS transistors have different electrical characteristics that allow for faster response and smaller compensation capacitances.
Solution Approach 2:
The patent inverts the conventional approach by using NMOS instead of PMOS as the main power device. This inversion of the standard design paradigm allows the circuit to achieve superior performance in terms of settling time and area efficiency, as NMOS transistors provide better control and faster switching characteristics for this application.
2Area of stationary object
If the voltage regulator circuit size is reduced, then the area footprint decreases, but the overhead current increases
Solution Approach 1:
The patent changes the transistor type parameter from PMOS to NMOS, which fundamentally alters the current-voltage characteristics of the power device. This enables the circuit to maintain low overhead current consumption while achieving a compact area footprint, as NMOS transistors offer better control over current flow and reduced leakage.
3Speed
If fast settling is achieved, then the response time decreases, but the power supply rejection ratio may deteriorate
Solution Approach 1:
The patent changes the power transistor parameter to NMOS, which provides inherently better power supply rejection characteristics due to the negative channel type. This parameter change enables the circuit to achieve both fast settling times and excellent PSRR, as NMOS transistors have different noise and rejection characteristics compared to PMOS devices.
Data Source
AI summary
The disclosed voltage regulator circuit includes an NMOS as the main power device that is coupled to a regulated voltage output. A sensing circuit senses the regulated voltage output, and a reference voltage circuit supplies a correct bias to the flipped-source follower, which amplifies the sensed voltage output. A voltage inversion circuit such as a current mirror provides an inverting gain stage for the sensed voltage output, for driving the NMOS. Various other methods, systems, and computer-readable media are also disclosed.