Noble Metal Interconnect Resistivity Reduction via Barrier Layer Oxidation

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Solution Overview

Problem

As semiconductor devices approach 5 nm nodes, copper line resistivity increases, necessitating the development of methods to fabricate interconnects with lower resistivity to maintain performance.

Innovation Solution

A method involving the formation of intermediate semiconductor interconnects with a substrate, cap layer, and dielectric matrix, including trenches and vias, where a barrier layer and noble metal interconnect material are deposited, annealed, and planarized, followed by oxidation or removal of the barrier layer to lower resistivity, and a dielectric cap is applied to achieve lower resistivity interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper is used as interconnect material, then ease of manufacture is maintained, but line resistivity increases at 5 nm nodes

Engineering Contradiction:
Improveline resistivityVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the material parameter from copper to cobalt, which has inherently lower resistivity at small dimensions. This material substitution resolves the resistivity increase problem while the established deposition and annealing processes maintain manufacturing feasibility

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary annealing treatment to the cobalt interconnect structure before final processing. This pre-treatment optimizes the electrical properties and reduces resistivity early in the fabrication sequence, preventing subsequent resistivity increases

Inventive Principle:
Principle #10Preliminary action

2Reliability

If copper interconnects are used, then existing manufacturing processes are maintained, but surface scatter increases reducing performance

Engineering Contradiction:
ImproveperformanceVSAvoidsurface scatter effects
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the interconnect material from copper to cobalt, which exhibits different surface scattering characteristics. Cobalt's electronic structure and surface properties reduce surface scatter effects at 5 nm nodes, thereby improving performance without increasing device complexity

Inventive Principle:
Principle #35Parameter changes

3Reliability

If copper interconnects are used, then standard fabrication is maintained, but electromigration reduces reliability

Engineering Contradiction:
Improveelectromigration resistanceVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent substitutes cobalt for copper, changing the material parameter to one with superior electromigration resistance. Cobalt's higher melting point and stronger atomic bonds provide inherent protection against electromigration, improving reliability while maintaining compatibility with standard fabrication processes through adjusted deposition and annealing parameters

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method results in semiconductor devices with lower line resistivity than traditional copper lines, reducing surface scatter and electromigration, while maintaining performance and reliability.

Implementation Method 1

depositing a barrier layer along a top surface of the semiconductor interconnect device

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

annealing the metal interconnect material

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

depositing a dielectric cap on a set of outer surfaces of the barrier layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS10679937B2Devices and methods of forming low resistivity noble metal interconnect
Publication Date: 2020.06.09 GLOBALFOUNDRIES US INC
  • US10679937B2 patent drawing
  • US10679937B2 patent drawing
  • US10679937B2 patent drawing

AI summary

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.