Network-on-Chip Memory Banking for Faster ML Data Access

The patent divides the memory system into multiple independent memory banks (first memory bank, second memory bank, third memory bank) that can be accessed in parallel. Each memory bank operates independently with its own control logic, allowing simultaneous data operations without interfering with each other. This segmentation eliminates the bottleneck of single memory access and reduces memory access overhead while supporting large-scale parallel computation.

The patent extracts the data access control logic from complex shared storage instructions and implements dedicated control circuits for each memory bank. These control circuits directly manage data reading and writing operations without requiring complex instruction decoding, thereby simplifying the access process and significantly improving data reading/writing efficiency while maintaining full data manipulation capability through the control logic.

The patent implements multiple memory banks that can be accessed simultaneously by different computation devices. Each memory bank maintains a simple structure, but the parallel access capability of multiple banks collectively provides high-speed data access. The system controller manages the parallel operations across banks, achieving high data access speed without complicating individual memory bank structures.

The patent introduces a controller as an intermediary between computation devices and memory banks to manage broadcast and multicast operations. The controller receives data from computation devices and intelligently distributes it to appropriate memory banks or multiple targets based on operation type. This intermediary approach simplifies the control logic by centralizing the decision-making process, while still providing sophisticated data distribution capability across the system.