Non-Continuous Seed Layer for Void-Free TSV Plating
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Solution Overview
Problem
As the dimension of through-silicon vias (TSVs) shrinks, it becomes increasingly difficult to form a void-free or seamless copper plated TSV structure due to challenges in depositing a continuous seed layer without resulting in high local deposition rates and resistance issues.
Innovation Solution
The method involves forming a TSV with an insulation layer lining the recessed via feature's sidewall, a continuous barrier layer covering the insulation, a non-continuous seed layer with a thicker portion at one end and a dielectric layer partially covering the sidewall, allowing for a conductive copper layer to fill the feature through a bottom-up electroless plating process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a continuous copper seed layer is formed inside the recessed via feature, then the TSV structure can be filled with copper through electroplating, but the thick seed layer around the TSV opening results in lower resistance at the opening and consequently high local deposition rates causing voids
Solution Approach 1:
The seed layer is divided into two distinct portions: a first portion disposed at one end of the recessed via feature and a second portion disposed at the other end, with a gap between them. This segmentation prevents the formation of a continuous thick seed layer that would cause high local deposition rates and voids, while still providing sufficient nucleation sites for copper electroplating to occur uniformly throughout the via feature.
Solution Approach 2:
The patent applies different seed layer configurations to different locations within the via feature. The first and second portions are positioned at opposite ends, creating localized seed regions rather than a uniform continuous layer. This local quality approach ensures adequate copper deposition initiation at critical locations while avoiding excessive seed material that would cause deposition anomalies in the middle region.
2Productivity
If the dimension of TSVs is reduced to achieve higher integration density, then more chips can be stacked and connected, but it becomes increasingly difficult to form a void-free or seamless copper plated TSV structure
Solution Approach 1:
By segmenting the seed layer into discrete portions at the ends of the via feature, the patent provides reliable copper deposition nucleation sites even in high-aspect-ratio, small-dimension TSVs. This segmentation approach scales well to reduced dimensions because it doesn't rely on forming a continuous seed layer that becomes increasingly difficult to control as via size decreases.
Solution Approach 2:
The patent changes the configuration parameter of the seed layer from continuous to discontinuous (segmented). This parameter change fundamentally alters the deposition behavior, allowing copper to plate uniformly from multiple localized nucleation sites rather than from a continuous thick layer, thereby maintaining void-free structure formation even as TSV dimensions are reduced for higher integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a void-free copper plated TSV structure by controlling seed layer deposition and plating processes, improving the reliability and efficiency of TSV fabrication.
Implementation Method 1
a conductive layer filling the recessed via feature
Implementation Method 2
a metal is filled into the vertical hole through an electroplating process to form a TSV
Data Source
AI summary
A through-silicon via (TSV) includes an insulation layer continuously lining a straight sidewall of a recessed via feature; a barrier layer continuously covering the insulation layer; a first portion of a non-continuous seed layer disposed at one end of the recessed via feature; a non-continuous dielectric layer partially covering the straight sidewall of the recessed via feature; and a conductive layer filling the recessed via feature.