Non-Lithographic 3D Conductive Elements on Sloped Surfaces
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Solution Overview
Problem
Current methods for forming conductive traces in semiconductor via formation and interconnection are inefficient and inaccurate, particularly when dealing with non-parallel surfaces, which hinders the development of compact and high-density chip arrangements necessary for advanced portable devices and data servers.
Innovation Solution
A method involving a substrate with a sloped surface and a sacrificial layer, where grooves are formed non-photolithographically, such as by laser ablation or mechanical milling, to create conductive elements that extend along the sloped surface, allowing for parallel electrical connections and reduced impedance between chip pads and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is used to form conductive traces along via walls or trenches, then conductive elements can be formed, but the method is inefficient and inaccurate when dealing with non-parallel surfaces and requires complex mask development and substrate repositioning
Solution Approach 1:
The patent replaces the photolithographic mechanical system (masks, alignment equipment, multiple exposure steps) with a direct deposition system that can conformally coat non-parallel surfaces. The conductive material is deposited directly onto the via walls and trenches without requiring photolithographic patterning, eliminating mask development and substrate repositioning complexities.
Solution Approach 2:
The patent changes the deposition parameters and methodology from planar photolithographic exposure to conformal deposition suitable for non-parallel surfaces. By modifying the deposition process to accommodate varying surface angles and geometries, accurate conductive trace formation is achieved on sloped via walls and irregular trench surfaces without the limitations of traditional photolithography.
2Reliability
If conventional via formation and interconnection methods are used, then electrical connections can be established, but the interconnections are not compact and have higher impedance, increasing signal propagation delays
Solution Approach 1:
The patent transitions from two-dimensional planar interconnections to three-dimensional conductive pathways. By forming conductive elements that follow the contours of via walls and fill trenches in multiple dimensions, the interconnection path is optimized for both length and impedance characteristics, enabling more compact and efficient signal transmission between chips.
Solution Approach 2:
The patent performs preliminary formation of conductive traces along via walls and within trenches before final via filling and chip assembly. This preliminary action allows optimization of the interconnection geometry in advance, ensuring compact pathways and low impedance are achieved before the chips are mounted and interconnected.
3Ease of manufacture
If photolithography is used for forming conductive elements, then patterning can be achieved, but the process is cumbersome requiring mask development that accounts for surface changes and substrate repositioning
Solution Approach 1:
The patent replaces the photolithographic mechanical system with a direct conformal deposition process. This substitution eliminates the need for mask fabrication, alignment, and multiple exposure steps, significantly simplifying the manufacturing process and reducing the time required to form conductive elements on non-parallel surfaces.
Solution Approach 2:
The deposition process is designed to automatically conform to the underlying surface geometry without requiring external patterning aids. The conductive material self-adjusts to the via wall slopes and trench configurations during deposition, eliminating the need for manual mask development that must account for surface changes and substrate repositioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient, compact, and low-impedance interconnects between chips, enhancing the bandwidth and reducing power consumption in complex electronic devices by overcoming the limitations of traditional photolithography-based methods.
Implementation Method 1
forming a groove in at least the sacrificial layer, the groove extending along at least the sloped surface, by removing a portion of the sacrificial layer by a non-photolithographic method
Implementation Method 2
forming a groove in at least the sacrificial layer, the groove extending along at least the sloped surface, by removing a portion of the sacrificial layer by a non-photolithographic method
Implementation Method 3
forming a conductive element having cross-sectional dimensions at least partly defined by the groove
Data Source
AI summary
A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.