Non-Overlap Summing Circuit for Glitch-Free Equalizer Output
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Solution Overview
Problem
Signal distortion occurs during electronic device communication due to channel response characteristics, leading to errors and misoperations, which existing equalizers struggle to fully compensate for effectively.
Innovation Solution
A summing circuit with a current summing circuit that generates glitch-free output current using a reference signal generator, non-overlap clock buffers, and current sources, ensuring that at least one switch in each current source is in an off-state to prevent glitches, and an equalizer incorporating this summing circuit to compensate for signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional equalizers are used to compensate for signal distortion, then signal distortion compensation is provided, but glitches occur in the output signal due to simultaneous switching of multiple current sources
Solution Approach 1:
The patent applies preliminary action by generating non-overlapping switching signals before the current sources switch. The switching signals are designed to ensure that when one current source is turning on, others are already off or in the process of turning off, preventing simultaneous switching glitches at the output node.
Solution Approach 2:
The patent implements periodic action through the sequential switching of current sources based on non-overlapping clock phases. Each current source operates in a specific time window within a periodic cycle, ensuring that their combined output remains stable without glitches caused by simultaneous transitions.
2Productivity
If multiple current sources are switched simultaneously to achieve high-speed signal processing, then processing speed is improved, but bias voltage nodes become unstable causing glitches
Solution Approach 1:
The patent uses preliminary action by pre-configuring the switching signals to activate current sources in a specific sequence rather than simultaneously. This ensures that bias voltage nodes have time to stabilize between switching events, preventing glitches while maintaining high processing speed through efficient sequential operation.
Solution Approach 2:
The patent applies dynamics by making the switching timing of current sources adaptive and sequential rather than static and simultaneous. The non-overlapping clock buffers dynamically control the switching phases, allowing the system to maintain stability during transitions while achieving high-speed operation through optimized timing sequences.
3Reliability
If non-overlapping switching signals are used to prevent glitches, then signal stability is improved, but additional clock buffers and control circuits increase device complexity
Solution Approach 1:
The patent applies segmentation by dividing the clock signal into multiple non-overlapping phases using separate clock buffers for each current source. This segmentation of the timing control allows independent optimization of each current source's switching timing, achieving glitch-free operation while keeping each buffer relatively simple in structure.
Solution Approach 2:
The patent implements universality by designing the clock buffers to perform multiple functions: generating non-overlapping switching signals, providing phase control for current sources, and stabilizing bias voltage nodes. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in overall device complexity.
Data Source
AI summary
Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.