Non-overlapping Impurity Layers in Semiconductor Devices
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Solution Overview
Problem
Thinning semiconductor substrates in PIN diodes used as power semiconductor devices can lead to breakdown due to high modulation levels and carrier concentration issues during recovery operations, degrading the safe operating area and requiring electron beam irradiation for lifetime control.
Innovation Solution
A semiconductor device structure featuring a semiconductor layer with a high impurity concentration first layer and surface-diffused second impurity layers, where the first layer is positioned between the second layers without overlapping, and additional impurity layers are introduced to control impurity concentrations and distances, preventing carrier concentration and stabilizing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If semiconductor substrates are thinned to reduce recovery loss, then forward voltage improves, but the PIN diodes break down due to high modulation levels and carrier concentration during recovery operations
Solution Approach 1:
The patent applies local quality by creating non-uniform impurity distribution through selective diffusion. The first impurity layers are diffused only in cell regions at specific depths, while termination regions maintain different characteristics. This localized impurity concentration control prevents carrier concentration issues during recovery operations while maintaining low recovery loss, resolving the contradiction between energy loss reduction and breakdown resistance.
Solution Approach 2:
The patent transitions from conventional two-dimensional layer structures to a three-dimensional impurity distribution approach. By controlling impurity diffusion in multiple dimensions (depth and lateral positioning), the patent creates overlapping and non-overlapping impurity layer configurations that simultaneously achieve low forward voltage and high breakdown resistance, overcoming the limitations of substrate thinning.
2Loss of energy
If electron beam irradiation is used for lifetime control to achieve low recovery loss specifications, then forward voltage improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent replaces the complex electron beam irradiation process with a simpler thermal diffusion process for lifetime control. By using controlled thermal diffusion to create specific impurity profiles, the patent achieves the same lifetime control and recovery loss reduction effects without requiring expensive and complex electron beam equipment, thereby reducing manufacturing complexity while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure prevents carrier concentration increases during recovery operations without electron beam irradiation, achieving low recovery loss and high forward voltage specifications, while stabilizing the breakdown voltage and reducing leakage current.
Implementation Method 1
a first impurity layer of the first conductivity type, the first impurity layer being partially diffused in an underside of the semiconductor layer
Implementation Method 2
a plurality of second impurity layers of a second conductivity type, the second impurity layers being partially diffused in a surface of the semiconductor layer
Data Source
AI summary
The technique disclosed in the Description adjusts a modulation level to enable prevention of partial concentration of carriers in a recovery operation. A semiconductor device includes: a semiconductor layer of a first conductivity type; a first impurity layer of the first conductivity type, the first impurity layer being partially diffused in an underside of the semiconductor layer and higher in impurity concentration than the semiconductor layer; and a plurality of second impurity layers of a second conductivity type, the second impurity layers being partially diffused in a surface of the semiconductor layer, wherein the first impurity layer is formed, in a plan view, between the second impurity layers and in a position that does not overlap the second impurity layers, and only the semiconductor layer exists between the second impurity layers in the surface of the semiconductor layer.