Non-Planar Ferroelectric Memory Cells Voltage Reduction
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Solution Overview
Problem
Current ferroelectric (FE) memory technologies face challenges in reducing critical voltage (Vc) without increasing cell size, and complex fabrication processes hinder large-scale adoption, affecting the commercial viability of FE memories.
Innovation Solution
Integration of non-planar FE or antiferroelectric (AFE) materials with transistor gates in memory cells, replacing conventional gate dielectric materials, allows for reduced critical voltage without size increase, using simple and low-cost fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar FE materials are used, then fabrication processes become complex, but critical voltage reduction is limited
Solution Approach 1:
The patent applies non-planar (curved/sidewall) FE material structures instead of conventional planar gate dielectrics. The FE material is deposited on sidewalls of trenches or recesses formed in the substrate, creating vertical or angled surfaces that increase effective area without increasing footprint. This curvature-based approach simplifies fabrication by using standard deposition techniques on pre-formed trenches, while simultaneously reducing critical voltage through enhanced electric field coupling with the channel.
2Reliability
If FE material thickness is increased to reduce critical voltage, then cell size increases
Solution Approach 1:
The patent transitions from two-dimensional planar gate dielectric structures to three-dimensional non-planar FE material structures with significant sidewall components. By depositing FE material on vertical or angled sidewalls of trenches, the effective FE area is dramatically increased without increasing the horizontal cell footprint. This dimensional transition allows critical voltage reduction through increased effective area while maintaining compact cell dimensions.
Solution Approach 2:
The FE material structure is nested within trenches or recesses formed in the substrate, creating a nested configuration where the FE layer lines the walls of the trench. This nesting approach allows the FE material to be positioned in three-dimensional space within the existing cell structure, maximizing the use of vertical space and increasing effective area without expanding the horizontal cell dimensions.
3Reliability
If non-planar FE materials are integrated with transistor gates, then critical voltage is reduced, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: first forming trenches or recesses in the substrate to define the FE material location, then depositing the FE material on the sidewalls, and finally completing the transistor gate structure. This segmentation allows each step to be performed using specialized techniques optimized for that specific operation, simplifying the overall process despite the non-planar geometry.
Solution Approach 2:
The trench structures serve multiple functions: they define the location for FE material deposition, provide the sidewall geometry that creates the non-planar structure, and act as the final FE material containment structure. This self-service approach eliminates the need for separate masking and patterning steps that would otherwise be required to create non-planar structures, simplifying the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient voltage reduction, maintains cell size, and simplifies fabrication, enhancing the commercial viability of FE memories by improving switching characteristics and reducing device variations.
Implementation Method 1
Memory cells with thin-film ferroelectric (FE) or antiferroelectric (AFE) materials pave the way for a promising technology
Implementation Method 2
Memory cells with thin-film ferroelectric (FE) or antiferroelectric (AFE) materials pave the way for a promising technology
Implementation Method 3
A FE or an AFE material is a material that exhibits, over some range of temperatures, spontaneous electric polarization, i.e., displacement of positive and negative charges from their original position
Implementation Method 4
Integration of non-planar FE or antiferroelectric (AFE) materials with transistor gates in memory cells, replacing conventional gate dielectric materials, allows for reduced critical voltage without size increase
Data Source
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Figure 3A~3C
AI summary
Memory cells with non-planar memory materials that include ferroelectric (FE) or anti-ferroelectric (AFE) materials are described. An example memory cell includes a transistor (110) provided over a support structure (302), where a memory material (312) is integrated with a transistor gate (304). The channel material (306) and the memory material (312) are non-planar in that each includes a horizontal portion substantially parallel to the support structure, and a first and a second sidewall portions, each of which is substantially perpendicular to the support structure, where the horizontal portion of the memory material is between the horizontal portion of the channel material and a gate electrode material of the transistor gate, the first sidewall of the memory material is between the first sidewall of the channel material and the gate electrode material, and the second sidewall of the memory material is between the second sidewall of the channel material and the gate electrode material.