Non-Volatile Memory Cell Two-Stage Programming for Over-Erase Control

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Solution Overview

Problem

Conventional 2T2C non-volatile memory cells have complex manufacturing processes and require multiple bias voltages for programming, erase, and read operations, which can lead to over-erase conditions and program failures due to excessive electron ejection.

Innovation Solution

A multi-procedure programming control method is introduced, involving a weak programming procedure followed by a strong programming procedure, using specific voltage combinations and time durations to avoid over-erase conditions and enhance electron injection efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional 2T2C memory cell structure with multiple bias voltages is used, then programming and erase operations can be performed, but over-erase conditions and program failures occur due to excessive electron ejection

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidover-erase condition

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The programming operation is segmented into two distinct phases: a first programming procedure with a first set of bias voltages followed by a second programming procedure with a second set of bias voltages. This segmentation allows control over the electron injection process to prevent over-erase conditions while ensuring reliable programming.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The programming process uses periodic application of different voltage sequences - alternating between the first programming procedure (with higher electron ejection) and the second programming procedure (with lower electron ejection). This periodic action balances electron injection to achieve reliable programming without excessive ejection that causes over-erase.

Inventive Principle:

Principle #19Periodic action

2Reliability

If multiple bias voltages are applied for programming operations, then program action can be achieved, but power consumption increases

Engineering Contradiction:

Improveprogram action effectivenessVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The power consumption is managed by segmenting the programming into two procedures with different voltage profiles. The first procedure uses higher voltages for effective electron injection, while the second procedure uses lower voltages to complete the programming with reduced power consumption, achieving both effectiveness and energy efficiency.

Inventive Principle:

Principle #1Segmentation

3Productivity

If conventional programming method is used, then programming speed can be maintained, but program disturbance and failure risks increase

Engineering Contradiction:

Improveprogramming speedVSAvoidprogram failure risk

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

By dividing the programming into two sequential procedures with different voltage characteristics, the method maintains overall programming speed while reducing failure risk. The first procedure performs the bulk of the programming work quickly, and the second procedure fine-tunes the state with lower disturbance, achieving both speed and reliability.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively switches memory cells from an erase state to a program state, reduces power consumption, and minimizes program disturbance and failure risks while ensuring efficient programming of multiple cells in an array structure.

Implementation Method 1

each memory cell comprises a floating gate transistor

Methodology Applied

Scientific EffectElectrical charge storage: Capacitance

Implementation Method 2

enhance electron injection efficiency

Methodology Applied

Scientific EffectElectron injection: Electron Beam

Data Source

PatentUS12400716B2Memory cell and array structure of non-volatile memory and associated control method

Publication Date: 2025.08.26 EMEMORY TECH INC

AI summary

A memory cell is connected to a source line, a bit line, a word line, an assist gate line and an erase line. When a program action is performed, a weak programming procedure is first performed on the memory cell, and then a strong programming procedure is performed on the memory cell. When the weak programming procedure is performed, an on voltage is provided to the word line, a first program voltage is provided to the source line, a ground voltage is provided to the bit line, a first assist gate voltage is provided to the assist gate line, and a first erase line voltage is provided to the erase line. When the strong programming procedure is performed, a lower program voltage and a higher assist gate voltage are provided to the memory cell.