Non-Conformal SiN Cover Layer for Simpler CFET S/D Formation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The complexity of complementary field effect transistor (CFET) fabrication, particularly in the formation of source and drain (S/D) terminals, is high due to the need for multiple process steps and modules, which increases costs and reduces efficiency.

Innovation Solution

A method for processing CFET devices that reduces complexity by forming fin structures with layer stacks, creating gate structures around them, forming preliminary fin cuts, and applying a non-conformal cover layer that exposes bottom channel layers for S/D formation while preventing unwanted epi growth at the top.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If traditional CFET fabrication methods are used with multiple process modules for S/D terminal formation, then the source and drain terminals can be formed, but the fabrication complexity increases significantly

Engineering Contradiction:
ImproveS/D terminal formationVSAvoidfabrication process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent extracts and removes the complex CSP module from the fabrication process by using a non-conformal cover layer deposited directly on the fin structure. This cover layer is selectively removed in specific regions to expose channel layers, eliminating the need for the separate CSP deposition and removal steps while maintaining the protective function during S/D terminal formation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The non-conformal cover layer is deposited in advance before S/D terminal formation, providing pre-protection to the top channel layer. This preliminary protective action eliminates the need for post-protection measures and simplifies the overall process sequence by integrating protection and exposure steps into a single deposition and selective removal operation

Inventive Principle:
Principle #10Preliminary action

2Reliability

If additional cover spacer modules are used to protect top channels during bottom S/D epi growth, then unwanted epi growth is prevented, but the number of process steps increases

Engineering Contradiction:
Improveepi growth controlVSAvoidnumber of process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the protective function previously performed by the separate CSP module with the non-conformal cover layer. The cover layer serves dual purposes: protecting the top channel during S/D formation and defining the exposure regions for bottom channel access, thereby combining multiple functions into a single integrated structure and reducing process steps

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If spin-on-carbon deposition is used to protect bottom channels prior to CSP module deposition, then channel protection is achieved, but additional material costs and processing time are incurred

Engineering Contradiction:
Improvechannel protectionVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The non-conformal cover layer acts as a disposable protective element that is deposited, serves its protective function during S/D terminal formation, and is then selectively removed. This eliminates the need for expensive spin-on-carbon deposition and subsequent CSP module processes, reducing both material costs and processing time while maintaining reliable channel protection

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the CFET fabrication process by reducing the number of steps and modules required, thereby lowering costs and improving efficiency while preventing undesired epi growth during S/D formation.

Implementation Method 1

The cover layer can be formed by a plasma enhanced atomic layer deposition (PEALD) process

Methodology Applied
Scientific EffectPlasma enhanced chemical vapor deposition: Plasma Enhanced Chemical Vapour Deposition

Data Source

PatentUS20250151375A1Non-conformal plasma deposited SiN for ISP
Publication Date: 2025.05.08 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US20250151375A1 patent drawing
  • US20250151375A1 patent drawing
  • US20250151375A1 patent drawing

AI summary

A method for processing a CFET device is provided that includes: (i) forming a fin structure that includes a first layer stack below a second layer stack, the first layer stack including a first channel layer and the second layer stack including a second channel layer; (ii) forming a set of gate structures around the fin structure and perpendicular to the fin structure and spaced apart from each other, the set of gate structures covering the fin structure in channel regions and exposing the fin structure in fin cut regions that alternate with the channel regions; (iii) at least partially removing the fin structure in the fin cut regions to form preliminary fin cuts; and (iv) forming a cover layer which partially covers side walls of recess(es) formed by the preliminary fin cuts