Non-Linear Polar Multiplier Cell With Integrated Majority-AND Logic
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Solution Overview
Problem
Existing circuit architectures for multiplier cells, particularly in CMOS logic, face challenges in reducing power consumption and area due to the increasing number of transistors required.
Innovation Solution
The implementation of a multiplier cell using non-linear polar material-based majority gates and threshold gates, which integrate majority and AND functions, reducing the need for switching transistors and minimizing interconnect routings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional CMOS logic gates (AND, OR, XOR) are used to build a multiplier cell, then the circuit can perform the required logic functions, but the number of transistors increases, leading to increased power consumption and area
Solution Approach 1:
The patent merges the majority gate and AND gate functions into a single integrated structure using non-linear polar material. The majority gate with three inputs (A, B, C) combined with a fourth input D through the non-linear polar material effectively performs AND logic, eliminating the need for separate AND gate transistors and reducing overall device complexity while maintaining power efficiency.
Solution Approach 2:
The non-linear polar material-based gate serves multiple functions simultaneously: it performs majority voting on three inputs, AND logic with a fourth input, and threshold-based switching. This multi-functionality replaces what would traditionally require multiple separate logic gates, thereby reducing the total transistor count and power consumption in the multiplier cell.
2Device complexity
If traditional CMOS logic gates are used to build a multiplier cell, then the circuit can perform the required logic functions, but the area occupied by the circuit increases
Solution Approach 1:
By combining the majority gate and AND gate into a single non-linear polar material structure, the patent reduces the number of discrete transistor components required. This integration directly reduces the layout area needed for the multiplier cell, as fewer separate gate structures and interconnections are needed compared to traditional CMOS implementations.
3Device complexity
If more transistors are used in the multiplier cell, then the logic functions can be implemented, but power consumption increases
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-based switching in CMOS to polarization-based switching in non-linear polar material. This parameter change enables lower operating voltages and reduced power consumption, as the non-linear polar material can maintain its state with minimal energy input, eliminating the continuous power consumption associated with CMOS transistor leakage and switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly lower power consumption and smaller area requirements compared to traditional CMOS multipliers, while also enabling low-voltage operation and non-volatile storage.
Implementation Method 1
a capacitor with non-linear polar material having a first terminal coupled to the common node and a second terminal providing a non-linear output
Data Source
AI summary
A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.